Sr. Physical Verification Engineer

Join Broadcom's ASIC implementation team as a key contributor in sign-off flows, focusing on physical verification, ESD checking, and package RDL routing. This role requires extensive experience in full-chip physical verification and strong scripting skills.

Responsibilities:

• Involved in sign-off flows including physical verification, ESD checking, and package RDL routing.
• Conduct full-chip physical verification (LVS/DRC/ANT/ERC).
• Understand and debug rule decks effectively.
• Perform block-level place & route tasks.
• Engage in full-chip implementation as needed.

Qualifications:

• Bachelor's degree with 12+ years of related experience or Master's degree with 10+ years of related experience.

Skills:

• Strong background in full-chip physical verification (LVS/DRC/ANT/ERC).
• Proficient in scripting languages such as Perl, Tcl, and/or Csh.
• Ability to understand and debug rule decks.
• Experience with block-level place & route.
• Familiarity with tools like Calibre, Redhawk & Totem, Cadence Virtuoso, Cadence Innovus, and Synopsys ICC2.