Sr. Physical Design Verification Engineer, Annapurna Labs

Annapurna Labs, a leader in silicon and software innovation, is seeking an ASIC Physical Design Integration and Verification Engineer to join its Cloud-Scale Machine Learning Acceleration team. This role focuses on the design and optimization of custom silicon and hardware for AWS Machine Learning servers, including AWS Inferentia and Trainium Systems. The ideal candidate will ensure the quality and manufacturability of complex semiconductor designs through rigorous physical verification processes.

Responsibilities:

• Define, execute, and optimize next-generation physical verification and integration methodologies using industry-standard EDA tools (Calibre, IC Validator).
• Drive chip-level physical verification sign-off and closure.
• Perform DRC (Design Rule Checking), LVS (Layout vs. Schematic), PERC (Programmable Electrical Rule Check) verification, and Fill insertion.
• Debug and resolve physical verification issues in collaboration with layout and design teams.
• Interface with foundries for rule deck updates and violation waivers.
• Develop and maintain verification runsets and methodologies.
• Support technology file development and qualification.
• Fine-tune cloud infrastructure to improve compute and storage utilization for physical design work.
• Mentor junior engineers on physical verification methodologies and closure.

Qualifications:

• BS + 10 years or MS + 7 years in Electrical Engineering, Computer Science, or a related field.
• 5+ years in physical verification for advanced technology nodes.
• Proven track record of successful tape-outs.

Skills:

• Experience in Python, Perl, or another scripting language.
• Expert knowledge of industry-standard physical verification tools (Calibre, IC Validator, PVS).
• Strong understanding of semiconductor manufacturing processes and design rules.
• Strong communication and collaboration abilities.
• Design Flow Knowledge: Understanding of backend physical design flows (FC/Innovus).