ASIC Synthesis and Timing Engineer

K2 is a pioneering space startup focused on developing the largest and highest-power satellites ever flown, backed by significant investment and contracts. The company aims to revolutionize satellite technology for missions ranging from Low Earth Orbit (LEO) to deep space, capitalizing on advancements in heavy-lift launch vehicles. K2 is seeking a motivated ASIC Synthesis and Timing Engineer to join their innovative team and contribute to the development of cutting-edge mixed-signal SoCs for next-generation satellite systems.

Responsibilities:

• Work on the RTL-to-Synthesis flow, performing synthesis at both block and top levels.
• Collaborate with the physical design team to integrate floorplan information for physical synthesis.
• Develop and maintain design methodologies, scripts, and automation to optimize performance, power, and area (PPA).
• Ensure timing closure and efficient design iteration in collaboration with front-end engineers.
• Drive timing closure across multiple voltage and process corners, including sign-off with foundry-qualified tools.
• Manage Lint, CDC, and UPF checks, driving collaboration to resolve issues.
• Develop a comprehensive formal verification methodology to ensure functionality between RTL and post-layout netlist.
• Guide external physical design partners and service vendors, ensuring alignment on milestones and quality standards.
• Work with EDA vendors to debug and optimize tool flows, and evaluate new methodologies.
• Support chip bring-up and debug in collaboration with post-silicon and test teams.
• Assist in product support through production and spaceflight.

Qualifications:

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
• 2+ years of experience in ASIC design for high-performance SoC blocks.
• Proven expertise in RTL-to-GDSII flows using industry-standard tools (Synopsys, Cadence, or Siemens).
• Strong hands-on experience with synthesis and constraints development.
• Deep understanding of physical design constraints for multi-clock, multi-voltage, and hierarchical SoCs.
• Experience with advanced FinFET process nodes.
• Prior experience in design convergence with offshore/outsourced PD teams or vendors.
• Ability to resolve formal verification issues and analyze VCLP issues regarding UPF.
• Experience with logic equivalence check debug and functional ECO development with minimal disruption.
• Familiarity with DFT integration and STA sign-off with functional ECO implementation.

Skills:

• Excellent communication and leadership skills.
• Strong cross-functional collaboration abilities.
• Experience with radiation-hardened or space-qualified ASICs (nice to have).
• Familiarity with physical design service vendor management or offshore collaboration (nice to have).
• Experience driving tapeouts through TSMC (nice to have).
• Knowledge of Gate-All-Around technologies (nice to have).
• Experience working in cross-functional, geographically distributed teams (nice to have).