ASIC Engineering Technical Leader

Join Cisco's Common Hardware Group (CHG) as a key contributor in designing and developing advanced ASICs for networking hardware that powers Cisco’s core Switching, Routing, and Wireless products. This role offers the opportunity to work on cutting-edge technology that impacts enterprises, service providers, and nonprofit organizations globally.

Responsibilities:

• Participate in chip architecture definition and discussions.
• Author design specifications and engage in micro-architecture specification reviews.
• Implement Verilog RTL to meet timing and performance requirements.
• Define, evolve, and support design methodology.
• Mentor junior engineers in project tasks and problem-solving.
• Collaborate with the verification team to address design bugs and ensure code coverage.
• Work closely with the physical design team to resolve timing and place-and-route issues.
• Triage, debug, and root cause simulation, software bring-up, and customer failures.
• Conduct diagnostic and post-silicon validation tests in the lab.

Qualifications:

• Bachelor’s degree in Electrical or Computer Engineering with 8+ years of ASIC Design experience, or a Master’s degree with 6+ years, or a PhD with 3 years in ASIC Design.
• Verilog/System Verilog programming experience.
• Experience in interactive and waveform debugging.
• Proven track record of delivering ASIC designs from specification to tape-out.
• Experience in architecture and micro-architecture development.

Skills:

• Experience resolving setup and hold timing violations with RTL modification.
• Scripting skills in Python, Perl, TCL, or shell programming.
• Strong troubleshooting and debugging abilities.
• Excellent written and verbal communication skills.