ASIC Diagnostic & Silicon Bring-Up Engineer

Eridu is a Silicon Valley-based hardware startup focused on pioneering infrastructure solutions that enhance AI data centers, aiming to improve AI performance by overcoming communication bottlenecks. The company has raised over $200M and is led by a team of experienced executives. Eridu is currently seeking a Senior ASIC Diagnostics Engineer to contribute to the post-silicon validation and debugging of high-performance ASICs.

Responsibilities:

• Develop diagnostics for early silicon validation and debug.
• Lead the bring-up of ASIC silicon on characterization and validation platforms.
• Validate power, reset, and clocking sequences, along with register access and initialization flows.
• Design and build Python-based diagnostic frameworks for register access, configuration management, and test orchestration.
• Develop diagnostics for SERDES links, Ethernet, PCIe, and UCIe/chiplet interfaces.
• Use SDKs and internal tools to generate traffic, verify data path correctness, and validate counters and statistics.
• Integrate and correlate behavior across RTL verification, emulation platforms, and silicon; develop correlation tools and methodologies.
• Perform deep debug across ASIC logic, interfaces, and firmware interactions; isolate functional mismatches, timing/clocking issues, and protocol failures.
• Develop automated diagnostics and integrate into regression frameworks and continuous validation pipelines.

Qualifications:

• Bachelor’s degree with 10+ years or Master’s degree with 5+ years of relevant experience.
• Strong experience in ASIC bring-up/post-silicon validation and hardware-software debug.
• Strong programming skills in Python (mandatory), along with C/C++ and scripting.

Skills:

• Experience building diagnostic frameworks, automation tools, and test orchestration systems.
• Experience with SERDES, UCIe/chiplet architectures, or networking ASICs.
• Familiarity with packet processor SDKs and emulation platforms.
• Experience with BER testing tools and SERDES tuning/margining.
• Exposure to CI/regression infrastructure for silicon validation.