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Analog IC Design Engineer

Published Date: September 28, 2026
WaveWorks Technologies Inc, Seattle, WA 98104
Job Description:

WaveWorks is a pioneering company specializing in wireless communication solutions for connected devices, focusing on low-cost, compact, and energy-efficient technologies. The company is expanding its engineering team and is seeking dedicated individuals to contribute to innovative projects.

Responsibilities:

  • Design ultra-low-power analog and mixed-signal blocks including bias and reference generation, low-dropout regulators, oscillators, and control loops.
  • Manage design at nanoamp bias currents, addressing leakage, noise, offset, and mismatch across various conditions.
  • Define power domains and management strategies for energy-efficient operation of each block.
  • Develop SystemVerilog and Verilog-AMS behavioral models for analog blocks and conduct mixed-signal simulations with digital designs.
  • Oversee layout design to minimize leakage and ensure matching, and review parasitic-extracted results.
  • Characterize silicon in the lab, correlate measurements with simulations, and integrate findings into subsequent revisions.

Qualifications:

  • BS in Electrical Engineering with 5+ years of analog IC design experience, MS with 3+ years, or a PhD.
  • Demonstrated experience in taking analog blocks through tapeout in a CMOS process and silicon bring-up.
  • Proficiency in Cadence Virtuoso and Spectre or equivalent tools, including corner and Monte Carlo analysis.
  • Experience in mixed-signal design and verification, including SystemVerilog and Verilog-AMS for simulations.
  • Strong understanding of subthreshold design, leakage, noise, and mismatch.

Skills:

  • Ability to write clear specifications and collaborate across analog, digital, and verification teams.
  • Experience in power management for low-power IoT or wearable devices.
  • Knowledge of low-power RF or wireless transceiver design, including PLLs and oscillators.
  • Familiarity with energy harvesting and battery-free system design.
  • Experience in advanced-node CMOS design for low leakage.

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