ASIC RTL Design Engineer, Interconnect & Memory Systems

Tesla's AI Hardware team is seeking an ASIC RTL Design Engineer with expertise in interconnect and memory systems to develop next-generation AI accelerators. This role involves working on custom ASIC data path elements, including NoC architectures and memory controllers, in a collaborative environment to support Tesla's autonomous driving and AI initiatives.

Responsibilities:

• Architect, design, and implement RTL for high-performance interconnect and memory subsystems.
• Develop microarchitecture specifications for memory controllers, MMUs, and arbiters.
• Define system-level functional requirements for SoC data paths focusing on throughput and scalability.
• Perform design analysis for memory and interconnect blocks, including timing closure and power optimization.
• Collaborate with cross-functional teams to integrate interconnect IP into full-chip designs and support silicon validation.
• Contribute to performance modeling and simulation of data path elements for AI hardware metrics.
• Stay updated on industry trends in ASIC design and propose innovations.

Qualifications:

• Degree in Electrical Engineering, Computer Science, or equivalent experience.
• 3+ years of hands-on RTL design experience in SoC interconnect or memory systems.
• Strong proficiency in Verilog or SystemVerilog for digital design.
• Solid understanding of AXI protocol and high-performance design techniques.
• Experience with synthesis, timing analysis, and linting tools.

Skills:

• Proven track record in Network on Chip (NoC) design and routing algorithms.
• Deep expertise in DMA engine design and memory controller architectures.
• Experience with high-performance SoC data path optimization for AI/ML applications.
• Familiarity with verification methodologies and scripting for automation.