ASIC Engineer Physical Design

Join Meta's Infrastructure organization as an ASIC Engineer specializing in Physical Design. This role focuses on high-performance AI/ML SoC and IP development, impacting the efficiency of data center applications. You will be responsible for the end-to-end physical design implementation, ensuring optimal performance and power efficiency in advanced technology nodes.

Responsibilities:

• Develop and own physical design implementation of low-power and high-performance designs.
• Resolve design and flow issues, identifying solutions and driving execution.
• Deliver physical design for end-to-end IP or ASIC/SoC integration, focusing on power and performance trade-offs.
• Define and implement schemes for improved performance and power efficiency.
• Collaborate with the RTL design team to drive physical aspects early in the design cycle.
• Interface with RTL design to resolve congestion/timing issues and implement functional ECOs.
• Automate and improve throughput and quality using EDA tool-based programming and scripting techniques.
• Interact with tool vendors for tool fixes and flow improvements, and evaluate new vendor tools.

Qualifications:

• Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field.
• 8+ years of experience in physical design and timing closure.
• Knowledge of RTL2GDSII flow and design tape-outs in 5nm or below process technologies.
• Experience with EDA tools like DC/Genus, Innovus/ICC2, Primetime, Redhawk/Voltus, or Calibre.
• Hands-on experience in SoC floor planning, place & route, and timing convergence of high-frequency designs.
• Knowledge of geometry/process/device technology implications on physical design.
• Experience with large SOC designs (>100M gates) with frequencies over 1GHz.
• Effective collaboration with internal and external teams across various functions and locations.
• Programming/scripting skills in TCL, Python, Perl, or Shell.

Skills:

• Full chip floor planning and partitioning.
• Low power implementation and power gating.
• High-speed clock distribution network planning and analysis.
• Static timing analysis and defining timing constraints.
• Circuit design and device physics knowledge.
• Experience in data-path intensive designs.
• Familiarity with 3D-IC technology and advanced packaging.
• Validation of Power Distribution Network (PDN), IR/EM, and thermals for 3D-IC.