ASIC Design Engineer – Fabric/Interconnect

Apple is seeking a highly skilled design engineer to join our team, focusing on the design and integration of coherent and non-coherent fabrics into subsystems or SoCs. This role is critical for delivering high-quality components at a rapid pace, requiring collaboration across various teams and a strong understanding of interconnect architectures.

Responsibilities:

• Design and integrate coherent and non-coherent fabrics into subsystems or SoCs.
• Own all aspects of RTL development, including design, templating, scripting, and RTL generation.
• Collaborate with other designers to achieve project goals.
• Integrate common/shared IP blocks and optimize memories/hard macros for the design.
• Work with front-end synthesis and STA teams to ensure timing requirements are met.
• Collaborate with power/performance and functional verification teams to ensure high-quality designs.
• Coordinate with multi-disciplinary groups to ensure timely delivery of designs with proper checks at every stage.

Qualifications:

• Minimum of a BS degree with 10 years of relevant industry experience.
• Knowledge of cache coherency protocols (MESI, MOESI, directory-based coherence) and memory hierarchy.
• Proven track record of delivering large, sophisticated designs for low power applications in high volume production.
• Experience working with synthesis, power, performance, and verification teams to deliver high-quality RTL designs on time.

Skills:

• Strong interpersonal skills for effective collaboration with diverse groups.
• Self-starter with high motivation and organizational skills.
• Schedule-driven with the ability to manage multiple tasks.
• Familiarity with front-end tools including lint, CDC, and synthesis.