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ASIC/FPGA Design Engineer [Compute Test Division; North Reading, MA]

Published Date: January 28, 2026
Teradyne, 600 Riverpark Drive, North Reading, MA 01864
Job Description:

Teradyne is a global leader in test and automation solutions, ensuring the reliability of electronic devices through innovative technologies. We are committed to fostering a diverse and inclusive work environment that empowers our employees to excel and innovate. Our Hardware Engineering team is looking for an FPGA/ASIC Design Engineer to contribute to the design and verification of cutting-edge products in a dynamic setting.

Responsibilities:

  • Derive requirements from higher-level specifications.
  • Write design documents for FPGA/ASIC projects.
  • Design and implement register-transfer-level (RTL) code using Verilog.
  • Utilize vendor IPs and industry-standard interface protocols in designs.
  • Employ digital simulation tools to verify designs.
  • Create physical design constraints for placement, timing closure, and CDC.
  • Implement designs into target technologies using synthesis and place and route tools.
  • Perform timing analysis using static timing analysis tools.
  • Conduct lab debugging of designs with equipment like Logic Analyzers and oscilloscopes.
  • Collaborate with logic designers, board designers, software designers, and ASIC designers.
  • Communicate project status to leadership.

Qualifications:

  • BS/MS in Electrical Engineering.
  • Minimum of 2+ years of industry experience.
  • Knowledge in digital logic design.
  • Experience writing RTL in Verilog HDL.
  • Familiarity with scripting languages such as Python, TCL, and Perl.
  • Experience with physical design tools from FPGA or ASIC vendors (Vivado or Quartus).
  • Ability to debug complex problems using software and hardware tools (debugger, JTAG emulator, logic analyzer, oscilloscope).
  • Excellent written and oral communication skills.
  • Familiarity with high-speed serial protocols including PCIe and Ethernet.
  • Familiarity with digital simulation tools such as Synopsys, Cadence, or Mentor.
  • Experience in high-speed digital circuit design.
  • Familiarity with C/C++ and source control tools.
  • Experience working in a Linux-based development environment.

Skills:

  • Digital logic design
  • RTL coding in Verilog
  • Scripting (Python, TCL, Perl)
  • FPGA/ASIC physical design tools
  • Debugging hardware and software
  • High-speed serial protocols (PCIe, Ethernet)
  • Digital simulation tools
  • C/C++ programming
  • Source control management
  • Linux development environment

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