ASIC Design Verification Engineer, Google Cloud

Join Google as an ASIC Design Verification Engineer, where you'll contribute to the development of cutting-edge TPU technology that powers AI/ML applications. This role involves shaping the future of AI/ML hardware acceleration and working on custom silicon solutions that enhance Google's data center capabilities.

Responsibilities:

• Plan the verification of complex digital design blocks and interact with design engineers to identify important verification scenarios.
• Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM).
• Identify and write coverage measures for stimulus and corner-cases.
• Debug tests with design engineers to ensure correct design blocks.
• Close coverage measures to identify verification gaps and demonstrate progress towards tape-out.

Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 1 year of experience in design verification.
• Experience with SystemVerilog/Verilog.

Skills:

• Master's degree or PhD in a relevant field preferred.
• Experience with UVM testbenches and methodologies.
• Experience developing and executing test plans.
• Familiarity with coverage analysis tools (e.g., Verdi, Questa).
• Proficiency in SystemVerilog, including object-oriented programming, SVAs, and functional coverage.
• Excellent problem-solving and debugging skills.