ASICS Design Verification Engineer

Qualcomm Technologies, Inc. is seeking a skilled engineer to join its Engineering Group, specifically within ASICS Engineering. The role focuses on the complete verification lifecycle for digital power IPs, emphasizing pre-silicon test planning, testbench development, and automation to enhance verification efficiency.

Responsibilities:

• Manage the complete verification lifecycle from system-level concept to tape out and post-silicon support.
• Develop comprehensive pre-silicon test plans for digital power IPs.
• Create testbenches using advanced verification methodologies such as SystemVerilog-UVM.
• Develop coverage and assertion models, and perform formal verification (property checking).
• Learn and implement power-aware UPF verification flows and methodologies.
• Automate processes to improve verification efficiency.

Qualifications:

• Bachelor's degree in Engineering, Science, or a closely related field.
• 2+ years of experience with ASIC design and verification tools, techniques, and methodologies.

Skills:

• Proficiency in digital design concepts and RTL languages (SystemVerilog, Verilog, or VHDL).
• Strong understanding of computer architecture fundamentals and object-oriented programming (C or C++).
• Experience in developing block-level testbench environments using SystemVerilog.
• Familiarity with verification methodologies such as UVM or OVM, and exposure to Assertion-based Formal Verification.
• Scripting/automation skills using Perl or Python.
• Knowledge of AMBA Bus protocol (AXI/AHB/APB) is a plus.