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CEO Talk: Stefano Perticaroli, RAME

This interview was help with Stefano Perticaroli, Ph.D. Eng., CEO at Radio Analog Micro Electronics srl.
 

 
Tell me a bit about your background? How did you first get started with Radio Analog Micro Electronics?
 
I completed my Ph.D in Electronics Engineering at DIET Sapienza Università di Roma

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On-chip ESD protection for 40nm and 28nm CMOS technology

Despite the rising cost for IC development, EDA tools and mask sets semiconductor design companies continue to use the most advanced CMOS technology for high performance applications because benefits like lower power dissipation, increased gate density, higher speed and lower manufacturing cost per die more than compensate the higher cost.
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Imec and Cadence Tape Out Industry’s First 3nm Test Chip

Silicone wafers in a carrier

The world-leading research and innovation hub in nanoelectronics and digital technologies, imec, and Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its extensive, long-standing collaboration has resulted in the industry’s first 3nm test chip tapeout. The tapeout project, geared toward advancing 3nm chip design, was completed using

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Sankalp Semiconductor to Present & Exhibit at Design & Reuse IPSoC Santa Clara 2018

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Sankalp Semiconductor, a design service company offering comprehensive digital & mixed signal SoC services and solutions, will be exhibiting at Design & Reuse IPSoC 2018 on 5th April in Santa Clara, California. Sankalp Semiconductor’s booth will be displaying expertise related to the digital, analog and mixed signal, custom layout, standard

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IP-Maker to launch new NVMe host IP Family

text labeled PRESS RELEASE

IP-Maker is introducing a new product line of NVMe Host IPs. In addition to the Easy NVMe Host IP, targeting embedded applications and launched in 2017, today IP-Maker announces the availability of two new products targeting data center applications: the Advanced NVMe Host IP, and the Multi Root NVMe Host

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Managing ASIC Qualification – A Quick Guide

Kid playing with jet

Many IC designers pay little attention to ASIC qualification and consequently pay high price and delays before the chip reaches to high volume. The mindset of experienced IC designers is considering IC quality (and reliability) through all phases of the IC design process. Today, more than ever, re-tapeout is costly

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