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Key ASIC Berhad Signs RM1.11 Million Contract to Jointly Develop AI-Driven, Ultra-Low Power RF Navigation Chip with Middle East Partner

press release chip

Kuala Lumpur, Malaysia – September 30, 2025 – Key ASIC Berhad (“Key ASIC” or “the Company”), a leader in ASIC design and innovation, has signed a contract worth RM1.11 million with a navigation systems company in the Middle East to jointly develop an AI-driven RF-integrated navigation chip.
 
 
The

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Analogue Insight IP Group Launches Analogue Insight SAFE in Portland, Oregon to Deliver Certification-Grade Security IP for Next-Gen SoCs and Chiplets

Security

PORTLAND, October 1, 2025 — Analogue Insight IP Group today announced the opening of Analogue Insight SAFE in Oregon, a new U.S. venture dedicated to developing and licensing high-assurance security IP for next-generation secure Systems-on-Chip (SoCs) and chiplet-based architectures. The new US entity will be led by Rachael J. Parker and David Johnston, expanding

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CAST Expands Security IP Portfolio with High Performance SM4 Cipher Core

news

Woodcliff Lake, New Jersey — September 30, 2025 — Semiconductor intellectual property (IP) provider CAST today announced the availability of a new SM4 Cipher IP Core, delivering compact, high-performance hardware implementations of the SM4 symmetric block cipher for both ASIC and FPGA designs.
 
SM4 is the Chinese national standard block cipher

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The 3 Hidden Risks That Can Derail Your IC Design Project! How to Avoid Them?

CPU chip installed on a computer motherboard

As more companies pursue ASICs to gain product-level differentiation, the ASIC road from concept to chip is paved with unseen challenges.
Many design teams, especially startups or system OEMs new to silicon, encounter the same pitfalls that delay projects, drain budgets, or derail product timelines.
 
Based on our experience

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Synopsys Collaborates with TSMC to Drive the Next Wave of AI and Multi-Die Innovation

press release wafer

Sept. 25, 2025 – 
SUNNYVALE, Calif. —   — Synopsys, Inc. (Nasdaq: SNPS) announced today its ongoing close collaboration with TSMC to deliver multi-die solutions, encompassing advanced EDA and IP products, that support TSMC’s leading-edge processes and packaging technologies, driving innovation in AI chip and multi-die design. The 3DIC Compiler exploration-to-signoff platform and IP, tuned for

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proteanTecs Announces Silicon-Proven IP on TSMC’s Advanced N2P Process

wafer

proteanTecs®, a global leader in advanced analytics for semiconductor health and performance monitoring, today announced the successful silicon-proven validation of its innovative IP-based health and performance monitoring technology at TSMC’s industry-leading 2nm (N2P) process node. The company is a member of the TSMC IP Alliance Program, a key component of

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