90nm is often misunderstood. It is sometimes treated like a “slightly smaller 130nm,” but in practice it behaves much closer to a transition node — especially in terms of cost sensitivity, design discipline, and backend impact.
This article explains how 90nm wafer and MPW costs really work, and when
65nm represents a transition point in custom silicon. It is often the first node where cost, complexity, and risk start to rise meaningfully, while still remaining accessible for non–mega-scale ASIC projects.
Because of this, cost assumptions at 65nm are frequently wrong — especially when teams assume it behaves like
130nm sits at an important intersection between mature analog processes and more integration-friendly digital nodes. It is often chosen when designers need more density than 180nm, without the complexity of advanced nodes. Cost at 130nm is often misunderstood — especially when comparing MPW and full mask options.
This article explains
180nm remains one of the most widely used semiconductor process nodes for analog, mixed-signal, power, and industrial ICs. Despite its age, it is still a first-choice node for many new designs. Cost is often cited as the main reason — but understanding what actually drives 180nm wafer and MPW pricing
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Many teams talk about doing an ASIC long before they know whether an ASIC is actually feasible. In practice, ASIC feasibility is not a yes/no question.
It is a balance of economics, risk, schedule, and technical reality.
This article explains what really makes an ASIC project feasible —
Booking an MPW shuttle is often seen as a safe first step toward silicon. In reality, MPW only reduces mask cost risk — it does not protect you from an unready design.
Many MPW failures happen not because MPW is the wrong choice, but because the design was not