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Number of 300mm Wafer Foundries Increases

Enormous financial and technology hurdles continue to plague the development of 450mm wafers. Ambitious goals to put 450mm wafers to use have been scaled back.  IC manufacturers are instead maximizing their manufacturing efficiency using 300mm and 200mm wafers.  IC Insights’ Global Wafer Capacity 2016-2020 report shows that

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Understanding Standard Cell Characterization

std-cell

Cell characterization is a process of analyzing a circuit using static and dynamic methods to generate models suitable for chip implementation flows.
 
Why is cell characterization needed?
 
No digital chip is possible without cell models. These cell models are produced by cell characterization using commercial softwares like guna.

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HDL Design House Opens New Office in Thessaloniki, Greece

Belgrade, Serbia – October 4th, 2016 – HDL Design House, provider of high performance digital and analog IP cores and SoC design and verification services, is pleased to announce the official opening of its new development center in Thessaloniki, Greece, to better serve and more efficiently handle the growing number

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X-FAB to Acquire Assets of Altis Semiconductor

X-FAB Silicon Foundries has today announced that it will acquire the assets of Altis Semiconductor, a specialty stand-alone foundry located in the Greater Paris area, out of insolvency proceedings.

With both companies serving complementary markets and applications, this acquisition enriches X-FAB’s offering. It roughly doubles the

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Top Semiconductor Foundries Growth 2015-2016 (per process node)

IC Insights recently released its September Update to the 2016 McClean Report. This Update included Part 2 of an extensive analysis of the IC foundry business.  An excerpt from the September Update, describing foundry sales by feature size, is shown below.
 
The following 2 charts show

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Is Charge Sharing Silently Killing your ASIC Design?

Sharing is caring, unless it is as vital as required charge to function your ASIC design. As we move down from 20nm and below on designs with low voltages, charge sharing is quickly becoming mission critical problem in high performance custom ASIC designs using dynamic logic. Moderate charge sharing may slow down your circuits,

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