Woodcliff Lake, New Jersey — September 30, 2025 — Semiconductor intellectual property (IP) provider CAST today announced the availability of a new SM4 Cipher IP Core, delivering compact, high-performance hardware implementations of the SM4 symmetric block cipher for both ASIC and FPGA designs.
SM4 is the Chinese national standard block cipher
As more companies pursue ASICs to gain product-level differentiation, the ASIC road from concept to chip is paved with unseen challenges.
Many design teams, especially startups or system OEMs new to silicon, encounter the same pitfalls that delay projects, drain budgets, or derail product timelines.
Based on our experience
Sept. 25, 2025 –
SUNNYVALE, Calif. — — Synopsys, Inc. (Nasdaq: SNPS) announced today its ongoing close collaboration with TSMC to deliver multi-die solutions, encompassing advanced EDA and IP products, that support TSMC’s leading-edge processes and packaging technologies, driving innovation in AI chip and multi-die design. The 3DIC Compiler exploration-to-signoff platform and IP, tuned for
proteanTecs®, a global leader in advanced analytics for semiconductor health and performance monitoring, today announced the successful silicon-proven validation of its innovative IP-based health and performance monitoring technology at TSMC’s industry-leading 2nm (N2P) process node. The company is a member of the TSMC IP Alliance Program, a key component of
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LONDON & TORONTO, Sept. 24, 2025 –
Alphawave Semi (LSE: AWE), a global leader in high-speed connectivity and compute silicon for the world’s technology infrastructure, today announced the successful tapeout of the industry’s leading 64 Gbps UCIe™ die-to-die (D2D) IP subsystem on TSMC’s 3nm process technology. Building on its 36
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Sept. 24, 2025 – CAMPBELL, Calif. – Arteris, Inc. (Nasdaq: AIP), a leading provider of system IP for accelerating semiconductor creation, today announced that NanoXplore, a French provider of radiation-hardened system-on-chip (SoC) FPGA technology, has licensed Arteris’ FlexGen smart NoC IP for its space designs. FlexGen will be used in the development
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