We love copper (Cu) wire. In fact, we already described in our post “Copper Wire (Cu) Reduces Package Cost” the cost advantages of copper wire bonding compared to Gold (Au) wire. Copper wire introduced some challenges to assembly houses (such as ASE, Amkor, STATS ChipPAC) but also offers a few
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Do you know someone that is not eager to reduce their ASIC production costs? I don’t. Some say that redesign changes can lead to significant cost reduction, for instance – using a more advanced silicon technology node to shrink the die size. True, but this is a really big, painful
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BGA substrate design is a critical step in the development of many ASICs, SoCs, processors, sensors, RF devices and high pin-count integrated circuits. The package substrate acts as the electrical and mechanical bridge between the silicon die and the printed circuit board. It routes signals from the die pads or
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MSL stands for Moisture Sensitivity Level. It represent the amount of time an IC can be exposed to ambient conditions and still be assembled on a PCB without being damaged.
When the antistatic bag is opened and the ICs are exposed to ambient conditions, the moisture in the air
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If you are debating which package type would fit best to your ASIC project, perhaps this article can help you narrow down the various options. In the semiconductor industry today there are three types of packages recommended for new designs:
QFN
Quad Flat No Leads. These are SMT packages,