Category Archives: IP Cores

Cadence Unveils Arm-Based System Chiplet

Arm logo

Cadence has announced a groundbreaking achievement with the development and successful tapeout of its first Arm-based system chiplet. This innovation marks a pivotal advancement in chiplet technology, showcasing Cadence’s commitment to driving industry-leading solutions through its chiplet architecture and framework.
 
The First System Chiplet
In a significant leap forward,

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Ultimate Guide: Embedded Non-Volatile Memory (eNVM)

reram operation

Embedded non-volatile memories (eNVM) are memory blocks that are directly integrated semiconductor fabrication on the same die. Since eNVM memories are non-volatile, the data is retained even when the power is off. In addition, eNVMs are reprogrammable and erasable multiple times. Compared to external non-volatile memory technologies, eNVMs have lower

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CAST Adds New SafeSPI Controller to its Functional Safety IP Core Product Line

SafeSPI CTRL

Woodcliff Lake, New Jersey — November 19, 2024—Semiconductor intellectual property provider CAST, in collaboration with Silesia Devices, today announced a new IP core that implements the Serial Peripheral Interface for Automotive Safety (SafeSPI), an emerging open standard that adds Functional Safety and interoperability features to the de-facto Serial Peripheral Interface

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Faraday Unveils HiSpeedKit™-HS Platform for High-speed Interface IP Verification in SoCs

Depositphotos

Faraday Technology Corporation (TWSE: 3035), a leading ASIC design service and IP provider, today announces the launch of its latest SoC platform, HiSpeedKit™-HS, designed to enhance and streamline the verification process for high-speed interface IP subsystems. The platform supports Faraday’s and third-party controller IP solutions, enabling comprehensive hardware and software

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Arm Files Lawsuit Against Qualcomm and Nuvia

Arm logo

Arm Holdings Plc has terminated its architectural license agreement with Qualcomm Inc., ending Qualcomm’s ability to use Arm’s intellectual property for chip design. The termination, reported by Bloomberg, follows a 60-day notice from Arm. This action escalates an existing legal dispute between the two companies, set to begin in Delaware

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VeriSilicon’s DeWarp Processing IP DW200-FS achieved ISO 26262 ASIL B certification

German luxury sport car

Shanghai, China, October 22, 2024–VeriSilicon (688521.SH) today announced that its DeWarp Processing IP DW200-FS has achieved ISO 26262 ASIL B automotive functional safety certification. The certificate was issued by TÜV NORD, an international inspection and certification institution.
VeriSilicon’s DW200-FS IP leverages advanced pixel mapping algorithms and cache-based data prefetch architecture,

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