Category Archives: IP Cores

CoreHW releases IP library with over 200 IP

CoreHW releases an IP library with over 200 silicon verified IP. Silicon proven solutions allow fast end-product development and implementation. The IP library gives a comprehensive look to company’s IP range and makes it easier and faster for customers to start their ASIC design process.
 
The IP listed in

MicroBT employs Moortec’s 16nm Embedded Temperature Sensor in their HPC ASIC

Moortec, providers of complete In-Chip Monitoring PVT Subsystems today announced that Shenzhen MicroBT Electronics Technology Co., Ltd. have employed Moortec’s 16FFC Temperature Sensor IP in their latest high performance computing (HPC) ASIC.
 

 
HPC is highly intensive in terms of CPU activity and requires ever increasing levels of

Moortec’s 7nm In-Chip Monitoring Subsystem IP chosen by Esperanto Technologies to optimise performance and reliability in its high-performance AI Chip

Moortec Semiconductor Ltd, providers of complete In-Chip PVT Monitoring Subsystems announced today that Esperanto Technologies have selected their complete 7nm Embedded In-Chip Monitoring Subsystem IP for Process, Voltage and Temperature Sensing to optimise performance and increase reliability for their AI Supercomputer-on-a-Chip. Esperanto develops high-performance, energy-efficient computing solutions for Artificial Intelligence

CEO Talk: Randy Caplan from Silicon Creations

This interview was held with Randy Caplan, CEO at Silicon Creations.

Tell me a bit about your background?
 
[randy] I’ve actually spent my whole career in integrated circuit design.  I started right at the peak of the dot-com era, and followed the advice of the “experts” at the

PLDA and MegaChips announce a cooperation to design PCIe controllers and PCIe PHY IP on TSMC’s 16nm Process Technology

PLDA, the industry leader in PCI Express® IP solutions and MegaChips, a global semiconductor company specializing in ASIC Solution Services, today announced their collaboration to design a combined PCIe Controller IP and PHY IP solution. While the combination is currently targeting the TSMC 16nm process, the PCIe Controller/PHY solution will

Silicon Creations’ Fractional-N PLL Technology Leveraged at Israel’s Bar-Ilan University SoC Lab

Silicon Creations, a leading supplier of high-performance analog and mixed-signal intellectual property (IP), today announced that the SoC Lab at Israel’s Bar-Ilan University as part of the HiPer Consortium project has successfully integrated Silicon Creations’ LC and ring PLLs (phase lock loop) intellectual property (IP) in its SoC1 chip implemented in TSMC