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HDL Design House and Mentor Workshop at Aviation Electronics Europe 2018

May 24, 2018, anysilicon

HDL Design House, provider of digital, analog, and back-end design and verification services and products in numerous areas of SoC, will host a joint technical workshop with Mentor, a Siemens business, at the Aviation Electronics Europe conference on June 19th, 2018 at the MOC Event Center in Munich, at 4pm. The workshop presenters will be Ms. Olivera Stojanovic, Verification Project Leader at HDL DH, Mr. Ivan Ristic, Senior Verification Engineer, Mr. Jacob Wiltgen, Functional Safety Solutions Architect at Mentor, a Siemens business and Mr. Michael Bierl, Applications Engineer at Mentor, a Siemens business.

 

Reuse, a crucial part of constrained-random verification, has been widely applied in land-based commercial electronics for the last decade. The joint workshop focuses on the application of state-of-the-art verification techniques in DO-254 projects.

 

Presenters at the workshop will introduce constrained random verification, highlighting requirement traceability goals that are mandatory in safety-critical designs. The concept of verification IP will be explained, followed by an overview demonstrating how third-party reusable verification IP provides the features and ease of use to rapidly verify and certify industry-standard protocols. Thus, attendees will learn how to demonstrate that all protocol features have been exercised and the elemental analysis evidence required by the DER.

 

“The ongoing trend to add further degrees of automation in aviation systems has triggered exponential growth in IC complexity and additional challenges ensuring those devices operate without failure,” explains Wiltgen. “Mentor’s verification solutions have helped design teams worldwide develop innovative ICs in virtually every industry. These tools and techniques can also be applied by designers of aviation ICs to achieve to new levels of IC design innovation, while still adhering to required safety standards. At our workshop during Aviation Electronics Europe 2018, IC engineers will learn about the very latest techniques and technologies for addressing these critical industry challenges and trends.”

 

The workshop is taking place on Tuesday 19 June, 4pm, at the Aviation Electronics Europe, and is free to attend.

 

HDL Design House will also present a paper on the application of random verification in DO-254 projects on June 19that 2pm at the conference. For further questions, please visit the HDL Design House booth (#B36) or the Mentor demo within the Exhibitor Showcase.

 

For more information, please contact Milena Jovanovic, m-jovanovic@hdl-dh.com.

 

About HDL Design House:

 

HDL Design House delivers leading-edge digital, analog, and back-end design and verification services and products in numerous areas of SoC and complex FPGA designs. The company also develops IP cores, and component (VITAL) models for major SoC product developers. Founded in 2001 and currently employing 170 engineers working in three design centers in Serbia and Greece, HDL Design House’s mission is to deliver high quality products and services, with flexible licensing models, competitive pricing and responsible technical support. The company was awarded ISO 9001:2008 and ISO 27001:2013 certifications in December 2006 and has achieved certifications from Direct Assessment Services (DAS). HDL DH joined the ARM® Approved Design Partner program, through which leading SoC design houses are recognized by ARM as accredited partners in specific technologies and activities. For more information, please visit www.hdl-dh.com.

 

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