ASIC Analog Layout Engineer

Micron Technology is seeking an ASIC Analog Layout Engineer to contribute to the development of high-speed analog and mixed-signal circuits for its tester and controller IP. This role focuses on the physical implementation of ASICs, ensuring optimal performance and reliability in advanced semiconductor technologies.

Responsibilities:

• Develop high-quality custom analog and mixed-signal layouts for high-speed ASIC applications.
• Collaborate with analog design engineers to create efficient and manufacturable layout solutions and provide feedback on layout feasibility.
• Perform and debug physical verification checks including LVS, DRC, ERC, and antenna rule analysis.
• Optimize layouts for parasitics, signal integrity, electromigration, ESD robustness, and latch-up prevention.
• Contribute to layout methodologies, hierarchy standards, and process improvements that increase team efficiency.
• Develop automation, scripting, and AI-enabled solutions to improve layout productivity and workflow effectiveness.
• Troubleshoot and resolve layout environment, CAD, and tool-related issues.
• Support layout implementation for high-speed circuit blocks such as SerDes, PLL, DLL, transmitters, receivers, clocking circuits, analog front-end designs, and related PHY circuitry.

Qualifications:

• Bachelor's degree in Electrical Engineering or related technical field, or equivalent industry experience.
• Experience using Cadence Virtuoso or similar custom IC layout tools to develop custom analog, mixed-signal, or ASIC layouts.
• Experience performing physical verification activities including DRC, LVS, ERC, and antenna rule closure.
• Experience working with semiconductor process technologies and applying analog layout fundamentals to optimize circuit performance and manufacturability.

Skills:

• 4+ years of experience in custom analog, mixed-signal, ASIC physical design, or IC layout engineering.
• Master's degree in Electrical Engineering or related technical field.
• Experience with advanced process technologies including FinFET nodes of 16nm or below.
• Experience supporting high-speed analog circuits such as SerDes, PHY, PLL, DLL, TX, RX, clocking circuits, analog front-end designs, or related high-speed blocks.
• Experience with parasitic analysis and extraction tools such as Quantus Insight, ParagonX, or similar technologies.
• Experience developing automation solutions using SKILL, Python, PVL, or related scripting languages, including the use of AI-enabled tools to improve engineering productivity and workflow efficiency.
• Experience with advanced-node layout techniques, including high-speed CMOS and CML layout methodologies.