ASIC Engineer

Join Cisco's Common Hardware Group (CHG) as an ASIC Design Verification Engineer, where you'll contribute to the development of cutting-edge data center solutions. Collaborate with a team dedicated to designing and testing advanced ASICs that power Cisco's core networking products for various sectors worldwide.

Responsibilities:

• Architect, develop, and maintain Design Verification (DV) environment infrastructure for block, cluster, and top-level designs.
• Build DV environments from scratch for block and cluster levels.
• Develop and enhance test plans and tests for block and cluster verification using constraint-random and directed stimulus.
• Ensure comprehensive verification coverage through code and functional coverage implementation and review.
• Qualify RTL design by running Gate Level Simulations on netlists.
• Collaborate with designers, architects, and software teams to debug issues during post-silicon bring-up and integration.
• Support design testing in emulation environments.

Qualifications:

• Bachelor’s degree + 5 years of ASIC experience, or Master’s degree + 3 years of ASIC experience, or PhD + 0 years of related experience.
• Experience in System Verilog and UVM methodology.
• Experience building reusable and scalable test benches from scratch.
• Experience with scripting using Perl and/or Python.

Skills:

• Experience with forwarding logic, parsers, or P4.
• Experience using emulation platforms such as Veloce, Palladium, Zebu, or HAPS.
• Experience with formal verification tools (e.g., IEV or VC Formal).
• Familiarity with protocols such as PCIe, CXL, Ethernet, RDMA, DDR, or TCP.