Next-Gen System Cache ASIC Digital Design Engineer

Qualcomm Technologies, Inc. is seeking an ASIC Engineer to join its Engineering Group, focusing on the design and development of high-performance, low-power System-On-A-Chip (SoC) products. The role involves collaboration with cross-functional teams to drive innovation and optimize hardware design for next-generation technologies.

Responsibilities:

• Micro-architect, design, and validate RTL for SoC Interconnects, Cache, and memory subsystems.
• Identify advanced optimization techniques for hardware design to enhance performance, power efficiency, and cost.
• Evaluate hardware feasibility for complex algorithms and requirements.
• Develop microarchitecture specifications for new generation designs.
• Create RTL corresponding to the developed microarchitecture.
• Conduct verification and debugging activities throughout project cycles.
• Optimize silicon cost and improve clock speed.
• Troubleshoot silicon issues related to the design.

Qualifications:

• Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field with a GPA > 3.5; OR
• Master's degree in the same fields with a GPA > 3.5; OR
• PhD in a relevant field.
• 2 years of ASIC design experience with a Bachelor's; 1 year with a Master's; or relevant experience for PhD holders.

Skills:

• Experience in Verilog/SystemVerilog design and Synopsys synthesis.
• Knowledge of low power design and test plan development.
• Familiarity with Computer Architecture and Computer Arithmetic.
• Proficiency in C/C++/Python programming languages.
• Experience in designing RTL for CPU and cache controller blocks is a plus.
• Strong communication skills and a collaborative team spirit.