Published Date: July 06, 2026
Normal Computing Corporation, Palo Alto, CA•Hybrid work
Job Description:
Normal Computing is a pioneering company that develops silicon technology to harness thermal noise for computational purposes, achieving significant efficiency in AI inference. With a collaborative team across multiple global locations, Normal Computing is backed by substantial investment and is focused on innovative ASIC design and AI-native EDA systems.
Responsibilities:
- Design and verify digital logic for thermodynamic hardware.
- Write synthesizable RTL in SystemVerilog for various blocks.
- Author functional verification environments using UVM, cocotb, or formal tools.
- Collaborate with architecture to translate specifications into microarchitectures.
- Work with physical design on timing closure and floorplanning constraints.
- Develop and maintain simulation infrastructure and regression pipelines.
- Participate in design reviews and contribute to architectural decisions.
- Support tapeout preparation and post-silicon bring-up.
Qualifications:
- Hands-on experience with production RTL in SystemVerilog.
- Experience in authoring verification environments in UVM, cocotb, or formal tools.
- At least one tapeout experience from any company size.
- Ability to operate across design and verification disciplines.
- Experience with datapaths, pipelines, or custom logic with unspecified microarchitecture upfront.
- Strong debugging skills in simulation and formal verification.
Skills:
- Proficiency in SystemVerilog and RTL design.
- Knowledge of UVM and verification methodologies.
- Experience in ASIC or SoC design.
- Ability to collaborate with architects and physical designers.
- Familiarity with AI chip design and verification processes.
