We are looking for a Senior SoC Design Verification Engineer to join our team in Seattle, WA or Santa Clara, CA. This role involves defining and implementing SoC verification plans, building verification test benches, and developing functional tests. The ideal candidate will drive design verification to closure, collaborating with cross-functional teams to ensure high design quality and continuous improvement in verification methodologies. Candidates should have a strong background in ASIC development, with 8 to 10 years of hands-on experience in SystemVerilog and UVM methodology, as well as familiarity with ARM processor-based SoCs and AMBA protocols. Proficiency in EDA tools and scripting languages like Python and TCL is also required. At Capgemini, we prioritize employee well-being, offering flexible work arrangements, comprehensive healthcare, and various financial and social benefits to support our diverse workforce.
