Sr. Staff HW Engineer – ASIC Implementation

We are looking for a Senior Staff Hardware Engineer specializing in ASIC Implementation to lead digital implementation efforts for our DSP ASIC programs in Cleveland, OH or Los Gatos, CA. This hands-on technical leadership role involves coordinating with internal teams and external partners to ensure successful first-pass silicon delivery.

Responsibilities:

• Perform and debug lint, CDC, and RDC checks, developing automation and scripts for analysis.
• Drive RTL-to-synthesis implementation flows and develop supporting automation.
• Develop timing constraints (SDC) for backend implementation and timing closure.
• Conduct synthesis for design exploration and PPA optimization.
• Maintain power intent specifications (UPF) and support low-power implementation.
• Perform RTL power analysis and assist with gate-level power analysis and correlation.
• Analyze timing reports to identify and resolve timing violations.
• Collaborate with RTL engineers to implement necessary RTL changes for timing and power requirements.
• Lead design readiness reviews before backend implementation kickoff.
• Serve as the primary technical interface with external backend teams.
• Oversee backend place-and-route activities and guide implementation closure strategies.
• Review backend implementation metrics and track resolution of physical design issues.
• Support timing closure and design optimization across RTL and implementation flows.
• Ensure designs meet timing, power, and integration requirements before tapeout.
• Coordinate implementation activities across internal teams and external partners using project management tools.
• Interface with project management teams to develop and track implementation schedules.
• Identify and communicate technical risks impacting implementation schedules.

Qualifications:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of experience in ASIC digital implementation.
• Strong experience with RTL-to-synthesis flows (Design Compiler, Fusion Compiler).
• Deep understanding of static timing analysis and timing closure (PrimeTime).
• Experience with low-power implementation methodologies including UPF.
• Experience performing RTL power analysis and optimization (RTL Architect, PrimePower, PrimePower RTL).
• Experience debugging post-layout timing issues with backend teams.
• Experience supporting designs through successful ASIC tapeout.
• Strong scripting skills (Tcl, Python) for automation and analysis.

Skills:

• Familiarity with place-and-route and physical design flows.
• Experience working with external backend implementation vendors.
• Experience with high-throughput datapath or DSP-based designs.
• Familiarity with advanced technology nodes (7nm and below).