Staff Design Engineer [Low Power]

Qualcomm Atheros, Inc. is seeking an experienced ASIC Design Engineer to join its Integrated Wireless Technology team. The role focuses on developing low power micro-architecture and design for WiFi technology, SOC Design, and power reduction techniques. The candidate will be involved in the full ASIC development process, from specifications to post-silicon bring-up, and will work closely with the verification team.

Responsibilities:

• Develop technical specifications from architectural and systems requirements.
• Deliver detailed low power micro-architecture and design.
• Collaborate with the verification team to create verification plans and participate in the debug phase.
• Own design through the full ASIC development process including specification, RTL implementation, verification, synthesis, timing closure, emulation, and post-silicon bring-up.
• Conduct silicon power measurements, silicon debug, and power correlation.
• Perform full chip debug design using ARM IPs.

Qualifications:

• Bachelor's degree in Science, Engineering, or related field with 4+ years of ASIC design experience, or
• Master's degree in Science, Engineering, or related field with 3+ years of ASIC design experience, or
• PhD in Science, Engineering, or related field with 2+ years of ASIC design experience.

Skills:

• Experience in SoC low power micro-architecture and design methodology.
• Proficiency in Power Intent/Implementation, power estimates, and power analysis tools.
• Hands-on experience in silicon bring-up and debug.
• Familiarity with multi-domain clocking and AMBA bus protocols (AHB, APB, AXI preferred).
• Experience with ARM IP based full chip debug and PCIE/USB peripherals.