The key is to ask what “ASIC design cost” includes. An engineering quotation, an MPW prototype price and the cost of a qualified product in volume production describe different deliverables. Comparing them directly can make a realistic project look either surprisingly cheap or impossibly expensive.

How to read the numbers: The node budgets below are transparent planning scenarios, not a survey of supplier quotes. The prototype table contains published 2026 prices. The savings example is illustrative. The named industry case is documented, but its contract value is not public.

1. Define the budget before choosing a process node

For an initial business case, separate engineering work from third-party charges and production costs. Ask each bidder to use the same boundaries.

A working formula is:

Development budget = engineering + tools/IP + prototype silicon + package/test development + qualification + contingency

Then add the recurring cost of manufacturing the number of chips you expect to sell. Internal engineering time is still a cost, even when it is not on a supplier invoice.

2. Estimated ASIC design budgets by process node

The following scenarios are intended for 2026 budget planning. They use an assumed blended engineering cost of $12,000–$25,000 per person-month. This is a modeling assumption, not a measured global billing-rate range. A person-month is one engineer working for one month; it is not the project’s elapsed duration.

The engineering bands come from multiplying the stated effort by that assumed rate. The broader project envelopes add a rough allowance for tools, licensed IP, initial silicon, conventional packaging and initial test/bring-up. They exclude volume inventory, major software platforms, advanced HBM/chiplet packages, extensive qualification, royalties and contingency. Obtain separate quotes for those items.

Editorial estimates, not market averages or price guarantees. Project scope deliberately grows down this table; it is not a controlled comparison of the same chip at different nodes. A difficult 180nm analog design can cost more than a small 28nm digital block. Upper values are not ceilings.

Very large programs can exceed these envelopes. Arm’s 2023 IPO filing reproduced an IBS July 2022 model for advanced designs: approximately $48 million at 28nm, $449 million at 5nm and $725 million at 2nm. That model includes software and other broad development activities. These are historical analytical benchmarks, not 2026 foundry prices or universal costs for every ASIC.^[1]

3. Real published prices: prototype silicon in 2026

EUROPRACTICE publishes the following standard mini@sic prices. They buy specified prototype fabrication allocations, not complete chip-development projects. EUR values are kept in their original currency.

Source: EUROPRACTICE 2026 schedule/pricelist. Minimum areas, options and access conditions differ; this is not an equal-area node comparison. For TSMC 28/40/16nm, consult the listed on-silicon scaling rules. Extra area and services may add cost. The TSMC program describes access for academia, research institutes and spinouts; commercial eligibility must be confirmed. These prices do not establish engineering, packaging, test or production costs.^[2][3]

4. The main ASIC cost drivers

Specification, architecture and verification

The number of custom blocks, clock and power domains, operating modes, interfaces and exception cases drives engineering effort. A modest chip with precision analog requirements can be demanding despite a small transistor count. Agree measurable specifications and verification acceptance criteria before requesting a fixed-price proposal. Late changes can undo completed design and verification work.^[4]

IP reuse and commercial rights

Proven IP can reduce new design work, but it still needs integration and verification in the target system. Check whether a license covers your exact process variant and intended products, whether royalties apply, and whether you can transfer the design to another supplier. A free instruction-set architecture does not automatically provide a free, validated processor implementation.

Process choice and analog requirements

Choose the least expensive process that meets the complete product specification. High-voltage devices, embedded memory, RF options, analog matching and long-term availability may be more important than logic density. A smaller node can reduce digital area while increasing implementation effort or forcing extra external components.

Packaging, test and qualification

Package selection belongs in the architecture discussion. I/O count, thermal limits, signal integrity and memory interfaces constrain the choices. imec recommends developing package and silicon plans together because packaging affects feasibility and schedule.^[5]

Budget probe cards, load boards, test-program development and characterization separately from unit assembly prices. Automotive, medical, industrial or radiation requirements need a project-specific qualification and documentation plan.

Schedule, respins and commercial structure

An accelerated schedule can require more parallel staffing, additional tools and priority services. A respin may add design work, masks or shuttle charges, assembly and retesting. Ask what is included if first silicon misses an agreed requirement. Supplier-funded development may reduce your upfront payment while increasing unit prices or minimum purchase commitments; compare the total contract economics.

5. How to target a 30%–40% cost reduction

A 30%–40% saving is a possible optimization target for an over-specified or heavily customized starting plan. It is not a typical result established by the sources here, and it is not a guarantee. The opportunities must be measured against a fixed baseline with the same required product performance.

1. Challenge the node choice before design starts. Price a mature-node option if it meets power, speed, memory and interface requirements. Include the impact on die size and unit cost.
2. Reuse proven blocks and platforms. Replace unnecessary custom design with suitable existing IP. Include licensing and royalties in the comparison.
3. Freeze the specification early. Resolve package, pinout, test access and operating modes before implementation. Reuse verification environments while preserving coverage and sign-off criteria.
4. Use shared fabrication where appropriate. An MPW can lower initial fabrication expenditure. Confirm access, schedule and whether later production requires a dedicated mask set; deferred spending is not a lifetime saving.
5. Use existing tools and test infrastructure. Compare a partner’s established flow with buying new licenses and building a new test platform. Verify what the quoted fee includes.
6. Compare complete commercial offers. Evaluate development charges, unit prices, IP rights, minimum orders, warranties and support together.

Worked example: a modeled 35% saving on a 130nm ASIC

Consider a sensor-interface ASIC with a small controller, standard serial interfaces and a conventional package. The baseline assumes substantial bespoke development. The optimized plan uses validated IP and an existing implementation and test flow on the same node. Both plans retain the required specifications, verification coverage and validation deliverables.

This is an illustrative budget, not a completed customer project or supplier quotation. Savings depend on suitable reusable assets actually being available.

The fabrication saving assumes a smaller verified die footprint within the same MPW route, not an invented foundry discount. Lower IP fees assume a suitable bundled license. Engineering savings come from fewer new blocks and existing verification assets. The 15% contingency is only an illustration; price identified risks individually. Production masks, volume inventory and any additional qualification remain separate in both plans.

Do not add independent savings percentages together: IP reuse, fewer engineering hours and a shorter schedule often describe overlapping benefits. This example adds distinct dollar reductions, then divides by the original budget.

6. A real-life ASIC example — and a public cost model

Documented case: Teradyne

In a January 2026 case study, imec IC-Link describes Teradyne’s use of custom ASICs in automatic test equipment. Teradyne connects the investment decision to both development cost and unit cost at expected volume, with IC-Link helping manage manufacturing economics. The case documents a real application; it does not disclose a project price or a 30%–40% saving.^[6]

Published numerical example: a 65nm controller

Separately, imec published a 2024 illustration with $3 million NRE, a $0.60 ASIC unit cost and a $2.50 off-the-shelf MCU at one million units annually. It is an illustrative business case, not a named customer invoice or a 2026 quotation.^[7]

Simple break-even volume = $3,000,000 ÷ ($2.50 − $0.60) ≈ 1.58 million units

At one million units annually, that is roughly 19 months after production starts, before financing, taxes, development time and other system-cost changes. At lower volume, payback takes longer; if an ASIC replaces several costly components, it can be faster.

Arithmetic illustration only. Add the actual manufactured chip cost, royalties and any additional project costs.

7. What to send for an accurate ASIC quote

Give providers a short, consistent brief. A node is optional at the first discussion; performance and volume targets are more useful than selecting a fashionable process prematurely.

• Application and existing solution: the product, components or FPGA being replaced, and target BOM saving.
• Technical requirements: key analog specifications, digital throughput, memory, interfaces, voltage and power budget.
• Commercial targets: annual and lifetime volume, target packaged-and-tested unit price, and available development budget.
• Schedule: specification readiness, prototype deadline and production launch.
• Delivery scope: existing RTL or IP, package constraints, qualification needs, design ownership and manufacturing responsibility.

Ask for separate pricing for feasibility, design, IP, prototype silicon, package/test development, qualification and recurring production. Request a written assumptions list and compare the same deliverables before choosing the lowest number.

Frequently asked questions

Can an ASIC be developed for less than $100,000?

A small educational prototype, limited design engagement or heavily reused platform may fit below that figure. Treat a complete commercial ASIC at that price as a scope question: confirm who pays for engineering, tools, IP, silicon, packaging, testing and qualification.

Does a €10,609 28nm prototype mean the complete ASIC costs about €10,000?

No. That published mini@sic price covers a specific minimum fabrication allocation. The complete project requires additional work and services.

Is the most advanced node the cheapest at high volume?

Not automatically. Compare the entire system: die area, wafer price, yield, packaging, test, royalties, performance and amortized development cost. Analog or voltage constraints can favor a mature process.

Is saving 30%–40% realistic?

It can be a sensible target when the baseline contains avoidable custom work or unnecessary process complexity. A tightly optimized project may have much less room. Require an itemized revised budget and retained acceptance criteria.