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Tessolve Secures $75 Million From Vector Line Capital to Fund Semiconductor Acquisitions

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press release

Oct-12th-2026– Tessolve Semiconductor has raised $75 million from U.S.-based Vector Line Capital to support strategic acquisitions, expand its semiconductor engineering capabilities and strengthen its global footprint. The Bengaluru-based semiconductor engineering company said it is already in advanced discussions regarding multiple acquisitions that could close over the next two quarters.

Acquisitions to Expand Tessolve’s Semiconductor Capabilities

The new investment is intended to accelerate Tessolve’s expansion through acquisitions that add technical capabilities, broaden its service portfolio and strengthen its global presence. According to the company, several potential transactions are already at an advanced stage.

Tessolve was founded in 2004 and originally focused on silicon test engineering. Over the past two decades, it has expanded into a much broader semiconductor engineering business covering chip architecture, design, validation, testing and embedded systems.

That evolution reflects a broader trend in the semiconductor industry. As chip development becomes more complex, semiconductor companies increasingly rely on external engineering partners that can support multiple stages of the development cycle rather than providing a single isolated service.

Vector Line Makes Its First Investment in India

Vector Line Capital is a U.S.-based investment firm focused exclusively on semiconductors and the global chip supply chain. Its investment in Tessolve represents the firm’s first investment in India.

Vector Line joins Tessolve’s existing investors TPG and Novo Tellus. Analytics India Magazine reported that Vector Line manages more than $1.6 billion in capital and invests across the semiconductor industry.

Vector Line founder and CEO Geoffrey Baldwin said semiconductor products are becoming increasingly difficult to design, validate and test, which is driving leading technology companies to rely more heavily on engineering partners capable of supporting work across the entire development cycle.

Tessolve’s ability to operate at scale across several stages of semiconductor development was highlighted as one of the key reasons for the investment.

From Silicon Test to Complete Chip Development

Tessolve now provides semiconductor engineering services from early chip architecture and design through validation, testing and embedded systems. The company develops chips for applications including artificial intelligence, high-performance computing, analog and mixed-signal systems.

It also works with hyperscalers, established semiconductor companies, startups, foundries and OSAT providers. The company says it currently supports 18 of the world’s top 20 semiconductor companies.

Tessolve employs more than 3,500 engineers across 10 countries and operates nine laboratories worldwide. Its broad engineering footprint allows the company to support customers at several stages of the semiconductor product lifecycle.

CEO and co-founder Srini Chinamilli said the company has moved from silicon test engineering to designing and productizing complete chips for companies building AI infrastructure. He said that transition required sustained investment in engineering capabilities, platforms and talent before the current wave of demand emerged.

AI and Custom Silicon Are Driving More Engineering Demand

The timing of the investment is particularly relevant as AI infrastructure increases demand for custom silicon. Hyperscalers and system companies are developing more proprietary chips for AI, high-performance computing and data-center workloads, creating opportunities for external semiconductor engineering providers.

These projects can require support across architecture, RTL design, verification, physical implementation, post-silicon validation, test engineering and embedded software. Engineering companies that can cover several of these areas can reduce the number of suppliers a customer needs to manage and potentially shorten development schedules.

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