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The following infographics shows Synopsys’s mergers and acquisitions along the years from its very beginning. Synopsys was founded in 1986 by David Gregory, Aart de Geus and has been involved with many mergers and acquisitions.
The very recent large acquisitions include:
2008
Synplicity
ChipIT
2009
ChipIdea
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Calculating the number of Dies Per Wafer (DPW) is a very simple and straight forward task. It’s actually based on basic high school mathematics which are related to circle area formula, remember Pi?
Silicon dies which are placed on a wafer can also be described as many
The following infographics shows Cadence’s mergers and acquisitions along the years from its very beginning.
Cadence Design Systems was founded in 1988 by the merger of SDA Systems and ECAD and has been involved with 100 mergers and acquisitions. The very recent and large acquisitions are:
Year 2013
Tensilica
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Process Lots (or corner lots) are special-modified-wafers that help verifying chip design robustness to accommodate process variations that statistically occur in wafer production over the years.
One of the products that semiconductor foundries offer is process lots (also called: corner lots, split lots or skewed lots). Corner lots wafers are
I have the utmost respect for TSMC. For their advanced technology; for the quality of their products; for their ecosystem; and for their contribution to the industry. In fact, TSMC has become so big – that it will take a while until the second ranked foundry can catch up.
The
In 2005 I applied for a job in Singapore. The job required some technical and business skills and therefore the interview was a bit tricky.
One part of the interview related to estimating market size. They asked me to estimate the number of Piano Tuning companies which are currently active
The name leadframe (or lead-frame) is actually very accurate.
Leadframe is an alloy frame that consists of the package leads and the paddle. The silicon die is attached on the paddle and the leads are connected to the die with wirebonds. That’s it.
In the above
Early on in Chip projects, yield is not taken very seriously. The common thinking goes – anyhow there isn’t much to do as this early point of time. However, there are actually several things you can do even before the Chip design starts, which will translate to clear savings.
1-
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HTOL (High Temperature Operating Life) testing is a stress test defined by JEDEC to define the reliability of IC products, and is an essential part of ASIC qualification tests. This post provides a high-level overview of HTOL test. Obviously, you should refer to the standard if you plan to perform
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Semiconductor Assembly and Test Services are converting rapidly into a pure outsourcing mode of operation. While today perhaps only 50% of the market is using Outsourced Semiconductor Assembly and Test (OSAT, or SATS) this number is set to increase in the future.
While many of the low-end suppliers are