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Getting the Most out of IC Design Houses

In the field of IC Design, there are many companies that have unique focus and experience in designing integrated circuits, as well as being involved in the other aspects of IC design house elements, such as packaging, testing, validation, et cetera.
 
It may seem like a simple choice to

TSV is a business…Looking for wider adoption!

3D Through Silicon Vias (TSV) is in MEMS, CMOS Image Sensors and high-end applications. When will it be used for mainstream consumer applications?… All results are part of the new report released by Yole Développement (Yole): 3DIC & 2.5D TSV Interconnect for Advanced Packaging – 2014 Business Update. This technology

The Future of Power Management ICs – PMICs [infographic]

This is a guest post by Vidatronic which is a fabless semiconductor and systems company specializing in the design of advanced-architecture, energy-efficient power management solutions.

In the last few decades, technology has been growing at a spectacular rate. So, it only makes sense that the parts that make up our technology

Introduction to IP Lifecycle Management

This is a guest post by Methodics that delivers state-of-the-art semiconductor data management (DM)  for analog, digital and SoC  design  teams.

No doubt that by now you have noticed that IP Lifecycle Management is a key Focus for Methodics and is a cornerstone of our platform for IP creators and SoC Integrators. Also

Challenges in Measuring Theta jc for High Thermal Performance Packages

This is a guest post by Jesse Galloway and Ted Okpe of Amkor Technology. Article reprinted from May 2014 Electronics Cooling magazine.

One of the more challenging thermal resistance measurements to make for electronic packages is the junction-to-case resistance called Theta jc. The equation for Theta jc, equation (1), is straightforward.

Can you reduce cost and development cycle of your next ASIC?

Have you ever wondered about the possibility of minimizing risk, design time and production cost simply by working with different IC design or verification companies? Or whether you could make your current ASIC cheaper by changing your FAT (foundry, assembly, test) providers?
 
Actually it’s something you can do right

Don’t Get Critical IP Cores from a ‘Supermarket’

This is a guest post by PLDA which designs and sells intellectual property (IP) cores and prototyping tools for ASIC and FPGA

You are on a tight schedule for your next chip. Not wanting to reinvent the wheel, you plan to go to an outside vendor for some of your silicon

ASIC Design Flow – an Overview

Today, ASIC design flow is a very solid and mature process. The overall ASIC design flow and the various steps within the ASIC design flow have proven to be both practical and robust in multi-millions ASIC designs until now.
 
Each and every step of the ASIC design flow has

How to make THE difference in SoC power management architecture

This is a guest post by Dolphin Integration which provides IP core, EDA tool and ASIC/SoC design services

 
To reduce the Bill-of-Material (BoM) and to simplify their usage, System-on-Chips (SoC) become more and more complex due to the integration of a large number of features previously located on board. This increase

Choosing IP core – It’s not just the product, it’s the relationship

This is a guest post by PLDA which designs and sells intellectual property (IP) cores and prototyping tools for ASIC and FPGA

You are on a very strict schedule for your next chip. Not wanting to reinvent the wheel, you plan to go to an outside vendor for some of your