Get the semiconductor daily news directly to you by subscribing to our email list. For ASIC designer and managers, staying updated with the latest news, technologies, and trends is crucial. Here are the lastest news from the semiconductor industry.
May-30-2025 — Nvidia and AMD are preparing to release a new generation of scaled-back AI GPUs for the Chinese market in Q3 2025, according to supply chain sources. These chips are specifically designed to comply with increasingly strict U.S. export regulations while still supporting key Chinese AI frameworks like DeepSeek.
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Washington, D.C. — May 30, 2025 — In a significant escalation of U.S.-China technology tensions, the Trump administration has directed leading American electronic design automation (EDA) companies—Cadence Design Systems, Synopsys, and Siemens EDA—to cease sales of semiconductor design software to Chinese entities. This directive, issued by the U.S. Department of
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Munich, Germany – May 28, 2025 – Taiwan Semiconductor Manufacturing Company (TSMC) today announced the establishment of its inaugural European Design Center, set to commence operations in Munich during the third quarter of 2025. This strategic move underscores TSMC’s commitment to supporting European clients in developing high-density, high-performance, and energy-efficient
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MILPITAS, Calif. – April 9, 2025 – Worldwide sales of semiconductor manufacturing equipment increased 10% to $117.1 billion in 2024 from $106.3 billion in 2023, SEMI, the industry association representing the global electronics design and manufacturing supply chain, reported today. The data is now available in the Worldwide Semiconductor Equipment Market Statistics
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May-28-2025 — CAMBRIDGE, UK – EnSilica, a leading chip maker of mixed signal ASICs (Application Specific Integrated Circuits), is pleased to announce that it has established a new engineering hub in Cambridge, UK.
Drawing on Cambridge’s renowned semiconductor ecosystem, EnSilica has opened a new engineering facility in the city and
Shanghai, China — May 27, 2025 — Brite Semiconductor (Shanghai) Co., Ltd. (BriteSemi, 688691), a leading provider of custom ASIC and IP solutions, today announced the launch of Ternary Content-Addressable Memory (TCAM) IP developed on 28HKC+ 0.9V/1.8V platform. This IP has the features of high frequency and low power consumption. With the
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LONDON & BASINGSTOKE — 23 May 2025 — Analogue Insight Ltd. and Tetrivis Ltd. today unveiled a strategic collaboration to co-develop Eurytion RFK1, a 12 nm RF chiplet transceiver that delivers wide-band Ka/Ku operation with an integrated local oscillator and up to 2 GHz of instantaneous, fully-programmable bandwidth. Leveraging Tetrivis’
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What Is Wafer Testing?
Wafer testing—often called wafer sort or probe testing—is the process of electrically evaluating individual semiconductor dies directly on the wafer. Using precision probe needles to make contact with bond pads or dedicated test structures, wafer testing allows engineers to:
Verify Device
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What Is Wafer Probe?
Wafer probe (or wafer probing) refers to the electrical testing of semiconductor dies while they are still part of the wafer. By using microscopic probe needles to contact bond pads or built-in test points on each die, engineers can:
Verify functionality:
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Kaiserslautern, Germany – May 21, 2025 – Creonic GmbH, a leading provider of ready-to-use IP cores for ASIC and FPGA applications, announces the release of its new oFEC (Open Forward Error Correction) codec IP core. The solution supports next-generation optical and high-speed communication systems and is now available in both
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