Network-on-Chip IP Core (NoC IP)

NoC stands for Network on a Chip. This is a communication system housed on a single System on Chip (SoC) or integrated circuit. It is usually employed as an interconnect between various blocks on a SoC.



Multiple signals share the same wires and links on an NoC, allowing the various data links to operate at the same time on different data packets. This parallelism ensures that the efficiency and performance of the system improves with the increasing complexity of the communication network. As such, the entire communication between the various block of the chip takes place over a singular infrastructure.


NoC vs. Shared Bus


One of the primary differences between these two solutions is the purpose for which they have been created and used. A typical shared bus comprises of a number of connected blocks including the likes of computing cores, subsystems, and memories. All of these units and links work together as connections are established between them, in order to accomplish a particular task at hand.


A Network on a Chip, on the other hand, is designed to establish links or connections between the various blocks on the SoC without compromising performance. It is a system that reduces the need to have a plethora of different wire connections, each indicated for a different signal, by ensuring high data transfer speeds and reliable data transmission.


NoC IP Advantages


Normally, an integrated circuit (IC) employs the use of point to point connections, meaning each signal or connection is carried over one wire. This can make the design of the chip quite complex and dense, making it confusing and inconvenient for relatively larger designs and networks that will have to employ the use of multiple physical connections that will take up a majority of the tangible space on the chip as well as hamper the performance of the system as a whole.


With the employment of NoCs in the system, it becomes possible to significantly reduce the number of wires being used and eliminating backend wire routing congestion. Reduced density of the circuit also enables the user to better understand the routing and switching functions and simplifies the required hardware. The sparsity of the connections also reduces interference and makes the design much more scalable and power efficient. Another benefit of the sparsity is that it enables you to resolve issues with the timing closure with much more ease and simplicity putting in pipeline registers and slices at precise locations. Ultimately, with the simplification of the hardware needed to execute the switching and routing functions, SoCs that employ the use of NoCs also tend to reach higher operating frequencies.


NoC IP Core


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