Category Archives: IP Cores

eMemory’s NeoFuse OTP Qualifies on TSMC’s N3P Process, Enabling Secure Memory for Advanced AI and HPC Chips

Press Release PR

(Hsinchu Taiwan, June 26, 2025) eMemory announced that its one-time programmable (OTP) memory solution, NeoFuse, has achieved qualification on TSMC’s N3P process, an enhanced 3nm process for better power, performance and density. As eMemory’s first OTP IP qualified on the TSMC N3P process, NeoFuse OTP underscores the company’s leadership in providing

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Sofics Delivers Remarkable PPA & R Performance Near Physical Limits on TSMC 2nm Technology

press release

GISTEL, BELGIUM – June 25, 2025 – Sofics bv, a world leading solution provider specializing in physical layout and design, with a focus on the built-in robustness of integrated circuits that demand superior power, performance, and area (PPA), today announced the silicon validation of its IP for TSMC’s cutting-edge

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Creonic’s DVB-S2 and DVB-S2X IP Cores Now Support the New DVB-NIP Standard

press release

Creonic’s DVB-S2 and DVB-S2X IP cores now include support for the new DVB-NIP standard on physical layer — an important step toward seamless integration of satellite and IP-based network technologies.
 
The DVB-NIP standard is designed to facilitate the native transport of IP over satellite networks, extending the capabilities of DVB-S2X by streamlining packet-based

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Faraday Delivers Latest SerDes IP to Complete Interface Lineup on UMC’s 22nm Platform

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Hsinchu, Taiwan — June 24, 2025 — Faraday Technology Corporation (TWSE: 3035), a leading ASIC design service and IP provider, today announced the availability of its 10G SerDes IP on UMC’s 22nm process technology. Designed to meet the increasing demands of high-speed data transmission, the new SerDes IP supports a broad

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CAST Launches Multi-Channel DMA IP Core Ideal for Streaming Applications

press release

Woodcliff Lake, New Jersey — June 19, 2025 — Semiconductor intellectual property core provider CAST has introduced a new direct memory access (DMA) IP core that alleviates a system’s host CPU from the resource-intensive task of managing data transfers between system memory and multiple peripherals with streaming interfaces.
 
The

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MIPS and Cyient Semiconductor collaborate to bring Custom RISC-V-based intelligent power solutions to AI Power Delivery, Industrial Robotics, and Automotive

press release gpt

San Jose, CA & Hyderabad, India- June 12, 2025: Cyient Semiconductors Private Limited, a fast-growing custom silicon company based in Hyderabad, and MIPS, a global leader in RISC-V processor IP, today announced a strategic collaboration to develop domain-optimized ASIC (application-specific integrated circuit) and ASSP (application-specific standard product) solutions that leverage

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