Category Archives: Qualification

How to bulletproof your ASIC Design

February 11, 2016, anysilicon

crystal ball

As the ASIC design is moving towards maskset creation and tapeout, the cost of design changes are increasing exponentially.  It’s easier and cheaper to modify the ASIC design and even redo some of the chip architecture early the design stage. However it’s much more difficult and far more expensive after

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Low Parasitic HBM ESD Testing

September 14, 2015, anysilicon


The Human Body Model (HBM) Electrostatic Discharge (ESD) test is the oldest and most widely used ESD test in the electronics industry. The JEDEC HBM test isn’t static; it has been revised to keep up with the rapid changes in the semiconductor industry. The latest revision of the spec addresses failures

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CDM ESD Testing: Getting a Clearer Picture

June 19, 2015, anysilicon


Of all of the component-level ESD tests available, the CDM ESD (charged-device model) test is the closest to simulating real world events. CDM ESD testing simulates ESD charging followed by a rapid discharge, similar to what is seen in the automated handling, manufacturing, and assembly of IC devices. Unfortunately, the CDM

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Electrostatic Discharge vs Electromigration

January 28, 2014, anysilicon


This is a guest post by Naman Gupta, a Static Timing Analysis (STA) engineer at a leading semiconductor company in India.

Electrostatic Discharge and Electromigration might sound similar, but refer to two different physical phenomena. Let’s take them up one by one.
Electrostatic Discharge (ESD) is the large current flow between any

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What Is Latch Up and How to Test It

October 01, 2013, anysilicon

Latch up

Simply defined, Latch-Up is a functional chip failure associated with excessive current going through the chip, caused by weak circuit design. In some cases Latch-Up can be a temporary condition that can be resolved by power cycle, but unfortunately it can also cause a fatal chip failure.
CMOS Latch-Up
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What is a Burn-in Board?

April 29, 2013, anysilicon


Burn in Board is a printed circuit board which functions as a jig in the Burn-in process. The Burn-in Board is used as part of the ASIC reliability testing process during which components are stressed to detect failures. Burn in Boards consist of sockets to accommodate the tested ASICs and

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