In building integrated circuits (ICs) or ASICs, one area of concern is how they are protected from outside electrical sources. While most systems are geared towards power overloads, one source that may cause considerable damage is the electro-static discharge (ESD) that comes from the human body. To help test for
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Many IC designers pay little attention to ASIC qualification and consequently pay high price and delays before the chip reaches to high volume. The mindset of experienced IC designers is considering IC quality (and reliability) through all phases of the IC design process. Today, more than ever, re-tapeout is costly
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As the ASIC design is moving towards maskset creation and tapeout, the cost of design changes are increasing exponentially. It’s easier and cheaper to modify the ASIC design and even redo some of the chip architecture early the design stage. However it’s much more difficult and far more expensive after
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This is a guest post by Naman Gupta, a Static Timing Analysis (STA) engineer at a leading semiconductor company in India.
Electrostatic Discharge and Electromigration might sound similar, but refer to two different physical phenomena. Let’s take them up one by one.
Electrostatic Discharge (ESD) is the large current flow between any
Simply defined, Latch-Up in VLSI is a functional chip failure associated with excessive current going through the chip, caused by weak circuit design. In some cases Latch-Up can be a temporary condition that can be resolved by power cycle, but unfortunately it can also cause a fatal chip failure.
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Burn in Board is a printed circuit board which functions as a jig in the Burn-in process. The Burn-in Board is used as part of the ASIC reliability testing process during which components are stressed to detect failures. Burn in Boards consist of sockets to accommodate the tested ASICs and
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