ASIC Physical Design Manager

Keysight Technologies is a leader in technology innovation, providing advanced solutions in electronic design, simulation, and testing across various industries including communications, automotive, and aerospace. With a workforce of approximately 15,000, Keysight is committed to fostering a culture of creativity and belonging, enabling employees to thrive in their careers. The company is seeking an ASIC Physical Design R&D Manager to lead a team focused on developing next-generation Digital and Mixed-signal ASICs, ensuring high performance and efficiency in product development.

Responsibilities:

• Drive the physical design technical strategy across programs, focusing on floorplanning, power architecture, and implementation trade-offs to meet performance, power, and area targets.
• Lead, mentor, and develop a high-performing Physical Design team, setting clear expectations for technical rigor and execution.
• Oversee physical implementation for digital, mixed-signal, and third-party IP, including place and route, timing closure, and power closure.
• Coordinate with RTL/design, DFT/test, packaging, and systems teams for seamless handoffs and rapid issue resolution.
• Continuously improve the Physical Design flow, including methodology, automation, and best practices for quality and predictability.
• Lead physical verification and signoff processes, ensuring readiness for tape release with clear criteria.
• Act as the primary interface with external foundries, ensuring alignment on PDKs and tapeout execution.
• Manage project execution across the physical design lifecycle, including planning, resourcing, and risk mitigation.

Qualifications:

• B.S. or M.S. in Electrical Engineering or Computer Engineering (or equivalent experience).
• 7+ years of experience in digital ASIC physical design with successful tape releases.
• 5+ years of project/program management experience, including planning and cross-team execution.

Skills:

• Demonstrated leadership in mentoring and developing engineers.
• Expertise in physical implementation and layout methodology, including timing closure and optimization.
• Knowledge of DFT methodologies and their impact on physical design.
• Strong fundamentals in ASIC design concepts and CMOS/BiCMOS processes.
• Excellent teamwork and problem-solving skills with effective communication across stakeholders.
• Ability to drive change and influence cross-functional teams toward execution goals.
• Sound technical judgment under pressure, with a track record of effective PPA trade-offs.