ASIC Design Engineer

Blue Origin is seeking an ASIC Design Engineer to contribute to the design of digital IP blocks for advanced satellite communication ASICs as part of its TeraWave project, which aims to revolutionize space-based communications. This role offers an opportunity to grow technical skills in RTL design and collaborate across teams to deliver high-performance silicon for space and ground communication platforms.

Responsibilities:

• Support the design and delivery of ASIC IP blocks from specification through RTL release under senior engineers' guidance.
• Assist in defining microarchitecture for digital signal-processing and control logic blocks.
• Participate in design trade studies involving throughput, latency, area, power, and schedule.
• Collaborate with systems, algorithm, and architecture teams to translate communication requirements into hardware implementations.
• Work with verification, DFT, physical design, and firmware teams to support successful integration and tape-out readiness.
• Contribute to RTL development, test plans, and implementation reviews to maintain high design quality.
• Identify technical risks and communicate them to the team early in the development cycle.
• Learn and apply standard processes in coding, review, and debugging.
• Support post-silicon bring-up activities and assist in debugging lab or field issues.

Qualifications:

• BS or MS in Electrical Engineering, Computer Engineering, or related field.
• 0–2 years of ASIC digital design experience (internships, co-ops, academic projects, or research experience considered).
• Exposure to ASIC or FPGA development through coursework, projects, or internships.
• Foundational knowledge of SystemVerilog/Verilog RTL design and debug.
• Familiarity with digital design fundamentals, including synthesis and timing concepts.
• Awareness of PPA (power, performance, area) tradeoffs in digital design.

Skills:

• Strong communication skills and the ability to collaborate across multidisciplinary teams.