Sr. ASIC Design Engineer [Video Silicon IP] – Multimedia Lab

Join ByteDance's Video Silicon IP team in San Jose as an ASIC Design Engineer, where you'll contribute to the development of cutting-edge video codec hardware solutions. This role involves collaborating with a diverse team of experts to create efficient and scalable video processing IPs that serve billions of users globally.

Responsibilities:

• Design hardware accelerators for advanced video encoding and processing.
• Collaborate with architecture, algorithm, and verification teams to develop high-performance, low-power video processing IPs.
• Create ASIC designs for compressing and processing still images and videos.
• Develop micro-architectures to meet area, power, and performance targets for multi-standard codec cores.
• Translate codec standard specifications into implementable hardware architectures in collaboration with algorithm teams.
• Design and implement RTL (SystemVerilog/Verilog) for various video codec pipeline stages.
• Drive functional correctness with the verification team using UVM test benches; debug and close RTL coverage metrics.
• Understand synthesis, timing analysis, and CDC/RDC checks; collaborate with physical design on floor plan and timing closure.

Qualifications:

• M.S./Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
• 5 years of ASIC front-end design experience as a primary RTL owner.
• Proficiency in SystemVerilog RTL design or High Level Synthesis (HLS).
• Familiarity with UVM/DPI/C++.
• Solid understanding of VLSI design concepts including pipelining, clock gating, and memory architecture.
• Scripting proficiency in Python for EDA flow automation.

Skills:

• Experience with Video Codec standards (H.265/HEVC, H.266/VVC, AV1, VP9, H.264/AVC).
• Experience with ISP or machine learning-based image/video compression.
• Experience with FPGA prototyping for pre-silicon codec validation.
• Practical experience using LLMs (e.g., GitHub Copilot, Claude, ChatGPT) to assist RTL design workflows.