ASIC Packaging Signal/Power Integrity Engineer [Hybrid]

Cisco Silicon One is seeking a Signal and Power Integrity Engineer to join their specialized ASIC team in San Jose, CA. This role involves developing and verifying ASIC packaging for high-performance silicon devices that drive complex networks. The ideal candidate will have a strong background in signal and power integrity, high-speed design principles, and experience with industry-standard EDA tools.

Responsibilities:

• Develop, document, and implement design rules for ultra-high-speed signaling to meet power, performance, and area goals.
• Analyze substrate signal integrity (SI) and power integrity (PI), collaborating with the layout team to optimize solutions across interposer, substrate, and PCB.
• Design and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting.
• Collaborate with system partners, vendors, and design leads to resolve complex technical issues and achieve combined power and signal integrity.

Qualifications:

• Bachelor's degree in Electrical Engineering with 4+ years of relevant experience, or a Master's degree with 2+ years, or a PhD with no experience, or equivalent work experience.
• Expertise in high-speed design principles, including Transmission Line Theory and impedance network analysis, particularly for 56G PAM4 SerDes architectures.
• Experience with pre- and post-layout SI/PI simulations using tools like Cadence Sigrity and Ansys HFSS.
• Experience conducting layout reviews and physical design validation using Cadence APD and Ansys EM flows.
• Working knowledge of SPICE for circuit-level analysis.

Skills:

• Strong communication skills to articulate technical concepts to diverse audiences.
• Experience with high-bandwidth memory (HBM) and high-speed memory interface SI.
• Familiarity with die-to-die interfaces and advanced packaging techniques.
• Knowledge of Vector Network Analysis and basic IBIS.