Published Date: July 04, 2026
Collins Aerospace, 1010 Production Road, Fort Wayne, IN 46808
Job Description:
Collins Aerospace, a leader in aerospace and defense technology, is seeking a Senior ASIC/FPGA Verification Engineer to join their Applied Research and Technology Microelectronics Technology team in Fort Wayne, IN. This role involves developing cutting-edge defense solutions and requires an active U.S. government security clearance.
Responsibilities:
- Design and architect verification environments using SystemVerilog with OVM/UVM.
- Create written test plans, test cases, and track code and functional coverage.
- Develop testbenches for RTL block verification using VHDL or SystemVerilog.
- Collaborate with design engineers for ASIC/FPGA integration and validation.
- Mentor junior engineers and provide technical guidance.
- Lead project verification teams by planning activities and reporting status.
- Contribute to engineering estimates for new program pursuits.
Qualifications:
- Bachelor's degree in STEM or related field with 5 years of experience, or an Advanced Degree with 3 years of experience.
- Active U.S. government issued security clearance required prior to start date.
- U.S. citizenship is mandatory for security clearance eligibility.
- Experience in developing and simulating RTL designs using VHDL and/or Verilog.
- Proven ability to design and execute verification testbenches for RTL blocks using VHDL/SystemVerilog.
- Knowledge of chip-level verification methodologies including constrained-random testing and functional coverage.
Skills:
- Proficiency in revision control tools (e.g., Git, Subversion).
- Excellent communication and teamwork skills.
- Experience with high-speed digital interfaces (e.g., DDR, PCIe, Ethernet).
- Familiarity with ASIC/FPGA lab validation and debugging.
- Proficiency in ASIC/FPGA simulation and synthesis tools (e.g., QuestaSim, Synplify, Quartus, Vivado).
- Background in aerospace, defense, or mission-critical systems.
- Proficiency in Unix/Linux environments and scripting.