ASIC Engineer

Meta's Silicon Engineering organization is seeking an ASIC Engineer specializing in performance and modeling to develop custom silicon solutions for its AI and data center workloads. This role involves defining architectural performance analysis, pre-silicon modeling, and microarchitectural exploration to ensure silicon meets high throughput, latency, and efficiency targets.

Responsibilities:

• Define and own the performance modeling strategy for custom infrastructure ASICs, including simulation environments.
• Drive microarchitectural exploration and trade-off analysis across various domains to inform silicon architecture decisions.
• Develop and validate pre-silicon performance models predicting post-silicon behavior for data center workloads.
• Establish performance analysis methodologies and benchmarking frameworks across the ASIC pipeline.
• Collaborate with architecture, RTL design, and physical design teams to translate performance requirements into microarchitectural specifications.
• Partner with software and systems teams to optimize workload scheduling and firmware against silicon performance.
• Lead technical reviews and communicate performance modeling results to engineering leadership.
• Define long-term performance modeling infrastructure roadmaps, including tooling and simulation platform investments.
• Mentor engineers on performance modeling techniques and best practices.
• Identify and resolve performance gaps through root-cause analysis and model calibration.

Qualifications:

• Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field.
• 5+ years of experience in ASIC performance modeling or pre-silicon simulation for custom silicon designs.
• Proficiency in C++ and Python for developing simulation models and performance analysis tools.
• Experience with cycle-accurate or transaction-level performance models for complex digital systems.
• Experience with performance analysis of data center or AI workloads on custom silicon.
• Experience defining microarchitectural specifications and driving cross-functional alignment.

Skills:

• Familiarity with post-silicon performance validation methodologies.
• Experience developing Python-based automation pipelines for simulation and performance analysis.
• Knowledge of high-level synthesis and PPA-driven microarchitectural optimization.
• Experience building performance modeling infrastructure for hyperscale data center ASICs.
• Familiarity with hardware description languages like SystemVerilog or VHDL.