Senior RTL Design Engineer

Join Google's innovative team to develop custom silicon solutions that enhance direct-to-consumer products. Your expertise will contribute to creating cutting-edge hardware experiences that deliver exceptional performance and efficiency, aligning with Google's mission to organize the world's information and make it universally accessible and useful.

Responsibilities:

• Define detailed microarchitecture specifications for silicon subsystems and intellectual property blocks to meet performance, area, and power requirements.
• Integrate internal and external IP blocks into complex silicon designs and multi-component subsystems.
• Execute production-grade RTL coding, debug simulation issues, and conduct verification checks.
• Collaborate with validation teams on test plans and coverage analysis for subsystem and chip-level design verification.
• Drive technical alignment across multi-disciplinary engineering groups to resolve architectural issues and ensure successful product delivery.

Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience with IP Development or Integration.
• Experience in ASIC development with Verilog or VHDL.
• Experience with a scripting language such as Python or Perl.

Skills:

• Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, focusing on computer architecture.
• Experience with ASIC design methodologies for clock domain checks, reset checks, and low power design.
• Knowledge of processor cores, buses/fabric/NoC, debug/trace, interrupts, clocks/reset.
• Familiarity with high-performance and low-power design techniques.
• Understanding of ASIC Verification, DFT, synthesis, STA, or physical design.
• Knowledge of FPGA and emulation platforms.