ASIC & FPGA Design Engineer Sr – E3

Lockheed Martin is seeking an experienced ASIC & FPGA Design Engineer to join their Missiles and Fire Control department. This role involves designing custom analog and mixed-signal ICs for advanced defense systems, with a focus on layout flow from floorplan to tape out.

Responsibilities:

• Own the entire layout flow from floorplan through tape out.
• Collaborate with circuit designers to create high-performance, parasitic-aware physical designs.
• Operate in a dual tool environment (Synopsys Custom Compiler and Cadence Virtuoso).
• Drive physical verification closure (DRC, LVS, ERC) across multiple foundries.
• Create floorplans and optimize area, matching, signal integrity, and power delivery.
• Perform EMIR analysis to address IR drop and electromigration concerns.
• Develop and maintain layout methodology and automation scripts.
• Manage tape out sign off packages, including documentation and design rule decks.
• Mentor junior layout engineers and promote knowledge sharing.

Qualifications:

• Associate degree or higher in Electrical Engineering, Electronics Technology, Microelectronics, or a related field.
• 8+ years of experience in full-custom analog or mixed-signal IC layout design.
• Experience with process nodes from 130nm to 12nm, including BCD technologies.
• Proficiency in Synopsys Custom Compiler and Cadence Virtuoso layout environment.
• Experience with physical verification closure across multiple foundry processes.
• Ability to obtain a U.S. security clearance.

Skills:

• Bachelor's degree in Electrical Engineering or related field (preferred).
• Experience with EMIR analysis and mitigation techniques.
• Scripting or layout automation skills (SKILL, Tcl, Python, or Perl).
• Layout experience with precision analog blocks such as PLLs, ADC/DACs, LDOs, and amplifiers.