ASIC Engineer, Performance Architecture and Modeling

Meta's Silicon Engineering organization is seeking an experienced ASIC Engineer specializing in performance and modeling to develop custom silicon solutions for its AI and data center infrastructure. This role involves defining performance analysis methodologies, pre-silicon modeling, and collaborating with various teams to ensure silicon meets high throughput, latency, and efficiency targets.

Responsibilities:

• Define and own the performance modeling strategy for custom infrastructure ASICs.
• Drive microarchitectural exploration and trade-off analysis across various domains.
• Develop and validate pre-silicon performance models for data center workloads.
• Create low-level workloads and kernels for machine learning applications.
• Establish performance analysis methodologies and benchmarking frameworks.
• Collaborate with architecture, RTL design, and physical design teams to translate performance requirements into specifications.
• Partner with software teams to optimize workload scheduling and firmware against silicon performance.
• Lead technical reviews and communicate performance modeling results to leadership.
• Define long-term performance modeling infrastructure roadmaps.
• Mentor engineers on performance modeling techniques and best practices.
• Identify and resolve performance gaps through root-cause analysis.

Qualifications:

• Bachelor's degree in Computer Science, Computer Engineering, or a related field.
• 8+ years of experience in ASIC design or silicon engineering.
• 5+ years of experience in ASIC performance modeling or pre-silicon simulation.
• Proficiency in C++ and Python for simulation models and performance tools.
• Experience with cycle-accurate or transaction-level performance models for complex digital systems.
• Experience with performance analysis of data center or AI workloads on custom silicon.
• Experience defining microarchitectural specifications and driving cross-functional alignment.
• Familiarity with assembly programming languages and compiler technologies.

Skills:

• Proficiency in C++ and Python.
• Experience with SystemC for performance modeling.
• Knowledge of hardware description languages like SystemVerilog or VHDL.
• Experience with performance modeling infrastructure for hyperscale ASICs.
• Familiarity with post-silicon performance validation methodologies.
• Experience developing automation pipelines for simulation and performance analysis.