Senior ASIC Engineer

Join Cisco's Common Hardware Group (CHG) in San Jose, where we innovate hardware platforms that power core Switching, Routing, and Wireless products globally. As part of a creative team, you will contribute to the development of cutting-edge technology in the AI era, from design to production.

Responsibilities:

• Drive the definition, architecture, design, and verification of high-performance ASICs.
• Own complex or multiple functional areas within projects.
• Develop reusable code for future projects and create re-usable code.
• Debug at ASIC, software, and hardware levels.
• Lead design and verification work, solving block-level issues and participating in chip-level issue resolution.
• Conduct reviews and identify architectural concerns.
• Define new verification methodologies and assist in lab bring-up.
• Lead code reviews at the platform level.
• Identify, design, and implement power-saving solutions.

Qualifications:

• Bachelor's degree with 7 years of related experience, or a Master's degree with 4 years of related experience, or a PhD with 2 years of related experience.
• Experience with ASIC design and verification processes, including System Verilog, debugging, methodology, and tools.

Skills:

• Experience with dashboard management for regression, coverage, and DV statistics.
• Post-silicon lab bring-up experience.
• Experience leading verification methodology (in UVM) for clusters/subsystems or full chip level for ASIC.
• Familiarity with emulation platforms such as Veloce, Palladium, Zebu, or HAPS.
• Proficiency in Linux, C/C++, and/or Python/Perl.
• Knowledge in Networking.