ASIC/RTL Design Engineer for High-speed Interfaces

Qualcomm Technologies, Inc. is seeking experienced micro architect and digital design engineers for its Mixed-Signal IP team. The role focuses on developing high-performance, low-power interface IPs, including SerDes, DDR, and die-to-die interconnects, for various applications across Qualcomm’s product portfolio, such as mobile, compute, data center, and AI. Candidates will work collaboratively with cross-functional teams to architect, design, implement, and validate complex IP blocks, requiring a comprehensive understanding of the ASIC design flow and advanced semiconductor technologies.

Responsibilities:

• Architect and define digital design of high-speed interface IPs in collaboration with system architecture and analog design teams.
• Develop micro-architecture and implement RTL for complex mixed-signal IP blocks.
• Apply advanced techniques in computer architecture, digital signal processing, and ASIC design to enhance power, performance, and area (PPA).
• Utilize industry-standard ASIC design tools for lint checking, clock domain crossing analysis, design-for-test, synthesis, formal verification, and static timing analysis.
• Design and analyze DFT logic, including ATPG for stuck-at fault and transition delay fault coverage.
• Create comprehensive design documentation, including hardware specifications.
• Collaborate with the design verification team to define test plans, verify designs, and fix bugs.
• Support physical design team in floorplanning, placement, and timing closure of IPs.
• Assist in SoC integration and debug, including pre-silicon simulation and post-silicon bring-up.

Qualifications:

• Bachelor's degree in Science, Engineering, or related field with 4+ years of relevant experience, or a Master's degree with 3+ years, or a PhD with 2+ years of experience in ASIC design, verification, validation, or integration.

Skills:

• Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 7+ years of experience in RTL and ASIC design.
• 5+ years of hands-on experience in micro-architecture and digital design for mixed-signal IPs such as SerDes, DDR PHY, PLLs, DACs, ADCs, and sensors.
• Proficiency with industry-standard front-end ASIC design tools including VCS, Fusion Compiler, PrimeTime, Power Compiler, DFT Compiler, and Spyglass.