Staff ASIC STA Engineer

Tensordyne is an innovative AI system solution company focused on developing high-performance, low-power generative AI inference systems. With headquarters in Sunnyvale, CA, and Munich, Germany, and a remote workforce across North America and Europe, Tensordyne is committed to creating custom silicon, hardware, and software to accelerate multimodal generative AI inference at scale. The company values its employees, offering comprehensive benefits and a supportive work environment to foster creativity and innovation in AI technology.

Responsibilities:

• Lead ASIC physical STA design and engineering workflow development for generative AI inference products.
• Guide and assist colleagues in improving frontend physical design related to STA at both block and full-chip levels.
• Drive optimization, implementation, and timing exploration workflows for full ASIC chip STA flow.
• Innovate and improve scalable, reliable, high-performance systems and tools for next-generation products.
• Collaborate closely with ASIC team members to enhance design and verification workflows.

Qualifications:

• 10 years of hands-on ASIC engineering experience with VLSI/SoC chip physical design workflows.
• Deep knowledge of EDA tools like Cadence/Synopsys PrimeTime/Tempus and clock methodology.
• Experience in writing SDCs for high-speed IP interfaces such as PCIe and SerDes.
• Ability to lead backend design teams and address STA timing issues, clock trees, and timing ECO generation.
• Understanding of Genus/Innovus tool usage for STA analysis.
• Bachelor's or Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related field.

Skills:

• Strong analytical, written, and verbal communication skills.
• Ability to collaborate effectively within a global engineering team.
• Expertise in physical design knowledge for STA analysis.
• Proficiency in developing hierarchical constraints and timing closure processes.