Two years ago TSMC announced its plans to expand into IC packaging services. It is unclear how much these plans succeeded up till now, but it definitely seems that TSMC is now in an excellent position to take a big bite into the advanced IC packaging market, enter into direct competition
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Burn in Board is a printed circuit board which functions as a jig in the Burn-in process. The Burn-in Board is used as part of the ASIC reliability testing process during which components are stressed to detect failures. Burn in Boards consist of sockets to accommodate the tested ASICs and
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The following infographics shows Synopsys’s mergers and acquisitions along the years from its very beginning. Synopsys was founded in 1986 by David Gregory, Aart de Geus and has been involved with many mergers and acquisitions.
The very recent large acquisitions include:
2008
Synplicity
ChipIT
2009
ChipIdea
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What is a die per wafer calculator?
A die per wafer calculator is a tool used by chip designers and fabs to estimate how many individual dies (aka chips) can be cut from a single semiconductor wafer.
It’s like trying to fit as many square stickers as possible on
The following infographics shows Cadence’s mergers and acquisitions along the years from its very beginning.
Cadence Design Systems was founded in 1988 by the merger of SDA Systems and ECAD and has been involved with 100 mergers and acquisitions. The very recent and large acquisitions are:
Year 2013
Tensilica
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Process Lots (or corner lots) are special-modified-wafers that help verifying chip design robustness to accommodate process variations that statistically occur in wafer production over the years.
One of the products that semiconductor foundries offer is process lots (also called: corner lots, split lots or skewed lots). Corner lots wafers are