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Synopsys Collaborates with TSMC to Drive the Next Wave of AI and Multi-Die Innovation

press release wafer

Sept. 25, 2025 – 
SUNNYVALE, Calif. —   — Synopsys, Inc. (Nasdaq: SNPS) announced today its ongoing close collaboration with TSMC to deliver multi-die solutions, encompassing advanced EDA and IP products, that support TSMC’s leading-edge processes and packaging technologies, driving innovation in AI chip and multi-die design. The 3DIC Compiler exploration-to-signoff platform and IP, tuned for

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proteanTecs Announces Silicon-Proven IP on TSMC’s Advanced N2P Process

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proteanTecs®, a global leader in advanced analytics for semiconductor health and performance monitoring, today announced the successful silicon-proven validation of its innovative IP-based health and performance monitoring technology at TSMC’s industry-leading 2nm (N2P) process node. The company is a member of the TSMC IP Alliance Program, a key component of

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Alphawave Semi Taped-Out Industry Leading 64Gbps UCIe™ IP on TSMC 3nm for the IP Ecosystem, Unleashing Next Generation of AI Chiplet Connectivity

press release chip

LONDON & TORONTO, Sept. 24, 2025 – 

Alphawave Semi (LSE: AWE), a global leader in high-speed connectivity and compute silicon for the world’s technology infrastructure, today announced the successful tapeout of the industry’s leading 64 Gbps UCIe™ die-to-die (D2D) IP subsystem on TSMC’s 3nm process technology. Building on its 36

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Arteris Selected by NanoXplore for Space Applications

Launch.

Sept. 24, 2025 –  CAMPBELL, Calif. –  Arteris, Inc. (Nasdaq: AIP), a leading provider of system IP for accelerating semiconductor creation, today announced that NanoXplore, a French provider of radiation-hardened system-on-chip (SoC) FPGA technology, has licensed Arteris’ FlexGen smart NoC IP for its space designs. FlexGen will be used in the development

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EnSilica and Codasip announce strategic partnership

news

Sept. 23, 2025 – 
EnSilica and Codasip announce strategic partnership to bring CHERI cybersecurity to automotive, critical national infrastructure, defence and aerospace applications
 
Oxfordshire, United Kingdom and Munich, Germany –  EnSilica, a fabless supplier of mixed-signal and digital ASICs, and Codasip, a provider of functionally-safe and cyber-resilient RISC-V CPUs, announces

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Silicon Creations Announces 1000th Production FinFET Tapeout at TSMC and Immediate Availability of Full IP Library on TSMC N2 Technology

press release

Lawrenceville, GA , Sept. 18, 2025 –  Silicon Creations, a leading provider of precision IP for advanced SoC design, today announced its 1000th production FinFET tapeout at TSMC, alongside the immediate availability of a comprehensive library of IP on TSMC’s advanced N2P process node. The N2P offering includes a full suite of PLLs and clocking IP, such as free-running

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